STM32 MPUs

Hello ST team and community,I am developing a custom STM32MP257-based MPU board and I want to create a customized Linux OS for our own product.I would like to understand the officially recommended approach and the limitations of using OpenSTLinux/Yocto versus an Ubuntu 24.04 ARM64 root filesystem.My target hardware is:MPU: STM32MP257F Custom PCB/SOM Cortex-A35 used for Linux Cortex-M33 may be used for real-time firmware Custom DDR/LPDDR4 configuration Custom Ethernet/USB/SD/eMMC/UART peripherals Custom Device Tree generated/configured using STM32CubeMX Development host: Ubuntu 24.04 LTSI understand that ST's current Distribution Package supports STM32MP25x and allows users to create their own Linux distribution. Thank You,Vijaya.

Hello,We are assessing security maintenance for an STM32MP1 product using linux-stm32mp. Could ST clarify the following? Is the maintenance policy in the 2021 "FAQ: Updating OpenSTLinux" (https://community.st.com/stm32-mpus-61/faq-updating-openstlinux-19) still current? How are security fixes delivered after a release: through component branches, tagged minor releases, or another mechanism? Has ST published updated guidance in preparation for the EU Cyber Resilience Act? Does ST assess kernel.org CNA CVEs against its vX.Y-stm32mp branches? Are per-CVE affected/fixed decisions published anywhere, such as a vulnerability list, VEX document, or CVE_STATUS entries in meta-st-stm32mp? For security vulnerabilities in ST-specific kernel changes that have not been upstreamed, what is the CVE assignment and advisory process? Where are fixes announced? The FAQ describes 1.5 years of feature development, 2.5 years of corrections, and a possible additional year of vulnerability-related relea

I am going to build linux system on a board based on STM32MP257F and have read many kinds of related technical documents.In the process, a question bothers me. I want to modify only several components such as uboot and kernel in existing STM32MPU Distribution Package. To do that, the STM32MPU Developer Package is needed because their source cdoes and build tools are required. This is where the major problem lies. Those are as follows:To build the source files, what is used between Developer Package’s SDK and Distribution Package’s BitBake ? After the modified components are built anyway, how and where are their binary images added into the Distribution Package including their configurations ?I have read in the documents that interoperation between the Developer Package and the Distribution one is available.But, I have not found out its actual usage example.

Subject: STM32MP257F-EV1 (MB1936D) not booting after PA6/PA7 MDF1 rework + SAI2 speaker addition — no console output, no USB DFU enumerationBoard: STM32MP257F-EV1, board reference MB1936DBackground — MDF1 microphone rework:We were bringing up PDM microphone capture on MDF1 (channel 6, PA6=SDI6, PA7=CCK0). On this board revision, PA6/PA7 are hardwired only to the onboard RTL8211F Ethernet PHY (ETH3.TXD0/TXD1 via series resistors R169/R175) with no external header access. To route these pins to MDF1 instead, we physically soldered a wire tap onto R169 and R175, and disabled Ethernet in our device tree so MDF1 could claim PA6/PA7 without a pinmux conflict.Background — speaker interface addition (same device tree, added afterward):Separately, we added a playback path using a MAX98357A I2S digital audio amplifier driving a 4Ω/5W speaker, over SAI2A:- CN5 pin 12 (PJ11, SAI2_SCKA) -> MAX98357A BCLK- CN5 pin 35 (PJ3, SAI2_FSA) -> MAX98357A LRCLK- CN5 pin 38 (PJ12, SAI2_SDA) -> MAX9835

Hi!I think a have found a bug in CubeMX for STM32MP257F processor.If you go to RIF - RISAB - VDERAM. You will find that the region size can only be 0x21000. That's more than 128 kB, according to the data sheet.SYSRAM1, SYSRAM2, SRAM1, SRAM2, RETRAM have 0x20000 as maximum region size.Question: If this is a bug, then I want to send a PR to the Github ST repository of the MP2 firmware. Can you guide me where the code is so I can make a PR?

I am using the STM32CubeProgrammer v2.2.3 with MX66UW1G45G_STM32N6570-DK external loader for the STM32N6570-DK.After reloading the STM32N6570-DK demo that came with the kit, I get the following error message (see below). Most of the demo runs normally except the AI demo won’t run at all now (nothing on the display). LEDs LD3 and LD4 turn red only when the AI demo is selected from the menu. NOTE: I can download a new GUI from TouchGFX with no issues at all. Here is the log...09:05:48 : Disconnected from device.09:05:59 : UR connection mode is defined with the SWrst reset mode09:06:00 : Warning: Device changed, refreshing...09:06:00 : UR connection mode is defined with the SWrst reset mode09:06:00 : ST-LINK SN  : 002700193235510E3836373009:06:00 : ST-LINK FW  : V3J15M609:06:00 : Board       : STM32N6570-DK09:06:00 : Voltage     : 3.29V09:06:00 : SWD freq    : 8000 KHz09:06:00 : Connect mode: Hot Plug09:06:00 : Reset mode  : Software reset09:06:00 : Device ID   : 0x48609:06:00 : Revision

Hi ST Community,I’m looking for the schematic/reference design for B-LVDS7-WSVGA, or the LCD part number or datasheet of LCD used on this board.

Greetings,I have finished the schematics of my custom STM32MP13X based PCB, My aim with this PCB is to learn high speed digital circuit design & how the board bring up is done & various other things like loading RAM's timing information from an EEPROM to initialize RAM, etc.I would appreciate if my schematics could be reviewed & any potential issues could be pointed out before I start my PCB design (or worse, produce the PCBs) because I’m a student who’s funding this project from my part time job & I really don’t want to make an expensive mistake.The schematics are majorly based on STM32MP135-DK's reference schematics (MB1635) & I have attached the schematics (PDF) along with BoM file for package size information, etc.I would also like to mention that the schematics have been designed to keep costs low, This is also why most of the components will be sourced via LCSC & This is also why there’s no eMMC on-board. I also omitted the termination resistors on DDR bec

Hi,Does anyone know if there is a list of the operating systems supported on the Cortex-A35 cores of the STM32MP257 ? Any information or pointers would be welcome.Thanks!

STM32MP257F-EV1: SPI3 Slave Mode — NSS Pin (PB1) Fails to Claim Despite Correct ConfigurationSummaryOn the STM32MP257F-EV1 evaluation board, configuring SPI3 in slave mode (spi-slave;) works correctly for the SCK, MOSI, and MISO signals, but the NSS (chip select) pin — PB1, using the documented-correct AF1 alternate function — silently fails to be claimed by the pin controller. No error or warning is logged anywhere. All three other SPI3 pins on the same bus, using the same AF1 value, claim successfully.HardwareBoard: STM32MP257F-EV1 (MB1936) MPU: STM32MP257FAI3 OpenSTLinux version: 5.0.15-openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18 Kernel: Linux 6.6.116-stm32mp-r3What we are trying to doConfigure SPI3 as an SPI slave (spi-slave; device tree property) so the STM32MP2 can receive data from an external SPI master over the same bus/pins already used for a sensor (previously configured as SPI master).Configuration usedCustom pinctrl group (added to stm32mp25-pinctrl.dtsi):spi3_slave_pins

Hello ST Support Team,We are working with the STM32MP257F-EV1 evaluation board and have identified a hardware/firmware-level restriction preventing us from using the SPI8 peripheral from the Linux (Cortex-A35) side, despite correct device tree configuration.Board: STM32MP257F-EV1OpenSTLinux version: 5.0.15-openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18Kernel: Linux 6.6.116-stm32mp-r3The issue:When we enable the &spi8 node in our device tree (with correct pin configuration, matching the same pattern that successfully works for other SPI peripherals like SPI3), the driver never initializes at all. There is no error message, no warning, and no output anywhere in dmesg — the peripheral simply remains completely silent and unclaimed, as if the device tree node doesn't exist.What we've already investigated and ruled out:Device tree correctness — confirmed the node, pinctrl, and pin assignments are syntactically and semantically correct, following the identical working pattern used success

Hello ST Team,I am working on a design based on STM32MP257F and would like to better understand the Resource Isolation Framework (RIF) and resource ownership between the Dual Cortex-A35 and Cortex-M33 cores.I understand that peripherals can be assigned to different processing domains, but I am looking for a detailed reference that clearly defines:Which peripherals are typically operated by the Cortex-A35 and which by the Cortex-M33? Is there any official resource ownership matrix available for STM32MP257F? Can all GPIO banks  be assigned independently to either Cortex-A35 or Cortex-M33? Are there any peripherals that are exclusively accessible by one core and cannot be reassigned? How is ownership handled for the following peripherals? GPIO Ethernet MACs USB2.0 / USB3.0 FDCAN I2C SPI / OCTOSPI UART / USART SDMMC DDR Controller GPU / VPU / NPU LTDC / DSI / LVDS ADC / DAC Timers DMA / GPDMA Is there a document showing: Peripheral-to-core mapping Security attribution Trust

I’ve just recently started with the STM32 tool chain so some of these may be answered elsewhere. Platform is Debian.Some problems have been encountered due to the editor in STM Cube IDE doing unexpected things, one of which led to the loss of a considerable amount of code. In general the editor is a bit week compared with e.g. Sublime text   Your IDE designers should try that - when copying and pasting, the indentations are correct, with CUBE the text ends up over indented. I’m now editing in Sublime and then pasting the complete text into Cube.ST-link problem: This has a uart channel, on my STM32F4 Nucleo board, this is prewired to UART3 of the target, for printf type debugging. However, there is limited documentation on connecting a terminal to this UART (ST-Link PC end), and the listings in the /dev folder are :The debian terminal program “screen” will not connect to any of these. Also, on the redirection of printf on the target: most of the on-line resources for this topic indicate

Hi all,I am bringing up the Ethernet switch (ETHSW) on an STM32MP257F-DK, bare-metal on the Cortex-A35 (no OS), following RM0457 Rev 5.Ping works with the switch bypassed (ETH1 directly to the PHY), and ping also works under Linux with the switch enabled on the same board. In bare-metal switch mode, ARP works but ICMP never arrives.SETUP- ETH1 -> Port0 (internal, no PHY), PHY (RTL8211F, RGMII) on Port2, negotiated 100 Mbps full duplex- SYSCFG_ETHSWCR = 0x6   SYSCFG_ETH1CR = 0x12 - Init order:ETHSW reset -> clocks -> SYSCFG_ETHSWCR -> release reset -> pulse ETHSW_FES_GEN_CTRLR INIT_REQ (bit 15) -> then ETH1 clocks/reset/DMA- PORT0 UNDER MANAGEMENT,MII,100 MBPS- PORT2 UNDER NORMAL, MII,100 MPBS WHAT WORKS- Broadcast/multicast from the PC reach ETH1 (ETH1 MMC broadcast counter increments)- The board's ARP reply (unicast) leaves ETH1, crosses Port0 -> Port2 (Port0 RX_UNICAST=1, Port2 TX_UNICAST=1) [confirm in Wireshark that the PC actually receives it]- Dynamic MAC tab

Hi,I try to follow the instruction from this link to compile the “device-tree” again. First of all, the 3 primary components (FLASH- SOURCE- and SDK-x86 ...) are extracted under the WORKDIR, together with MyDeviceTree generated from the STMCubeMX. Next, the dedicated variables EXTDT_DIR, FWDDR_DIR, FIP_DEPLOYDIR_ROOT are set-up.I did also run the SDK environment to prepare for the next steps.Regarding “unpack and patch sources”, I follow the instruction line by line and did successfully.Then for the “regenerate the kernel DTB”, I got stuck at the line “make” the “.dtb” files. For this line, I changed the command as follow:MY_DEMO → MP15 (which is my project name) /linux → /kernel (since I couldn’t find the sub-dir “linux” in the DeviceTree directory) stm32mp135f → stm32mp157d -my_demo- → mp15→ Hence the file stm32mp135f-my_demo-mx.dtb will become stm32mp157d-mp15-mx.dtb, which matched with the stm32mp157d-mp15-mx.dts from the ../kernel directory.However I got the following errors and d

I am working with an STM32MP257F-EV1 Evaluation Board (board reference MB1936, target device STM32MP257FAI3) and am trying to debug a standalone bare-metal application running on the Cortex-M33 core directly over SWD using ST-Link.Current SetupBoard: STM32MP257F-EV1 Board reference: MB1936 Target: STM32MP257FAI3 Tools: STM32CubeIDE and STM32CubeProgrammer Boot configuration (SW1): Development boot Boot0 = 1 Boot1 = 1 Boot2 = 0 Boot3 = 0 JP3: No jumper fitted (STLINK-V3EC active) CubeIDE Debug Configuration: Load Mode = "thru JTAG/SWD link (Engineering mode)" Access Port = "8 - Cortex-M33" Debug interface = SWD I have also attached a screenshot of the debug error I am receiving.Current ObservationI am able to debug the Cortex-M33 successfully when the board is first booted from an SD card. After the SD-card boot completes, I can connect to and debug the M33 core from CubeIDE.However, my requirement is to debug the M33 without booting the board from an SD card, eMMC, or QSPI.Specif

Hi,I'm working on a custom STM32MP157C board with a Microchip LAN8742A PHY (RMII). Originally the board uses an external 50 MHz oscillator that feeds both the PHY and the SoC's PA1 (ETH1_RMII_REF_CLK) — the classic LAN8742A "REF_CLK In Mode" setup, same as ST's reference schematic. That works fine.I'm now trying to get rid of the external oscillator and have the SoC generate the 50 MHz REF_CLK itself instead, using RCC's CLK_ETH_PLL3Q — the setup ST documents in AN5031, Figure 45 ("RCC provides 50 MHz ETH_CLK"). For this test I desoldered the two series resistors that fed the oscillator signal in, isolated the oscillator, and bridged PA1 straight to the PHY's XTAL1/CLKIN through a wire + the same 22 Ω resistor as before. I also added st,eth-ref-clk-sel; to the ethernet node in both the kernel and U-Boot device trees, rebuilt and reflashed.Result: PHY never comes out of reset (phy_poll_reset failed: -110), and an oscilloscope on PA1 shows absolutely nothing — not even a weak or distorte

Hello,According to Table 56 (Output voltage characteristics for all I/Os) in the STM32MP213FAL datasheet, the maximum VOL is specified as 0.4V under high load conditions (IOL = 5.5mA to 20mA).In my application, the connected device has a strict VIL(Min) requirement of 0.35V. My actual load current is very low, around 10uA.While I understand that VOL should stay very close to 0V under such a low load due to the CMOS structure, the datasheet only provides the Max 0.4V limit.Strictly speaking, this does not show a match with my 0.35V requirement on paper.Could you provide any reference curves, typical characteristics, or internal RON (on-resistance) values for the I/O pins to confirm that VOL drops well below 0.35V under a 10uA load? Thank you in advance for your support. 

The STM32MP2 supports gstreamer. There is a version of Gstreamer for streaming through the WebRTC protocol.Another library for streaming though the WebRTC protocol would be LibWebRTC.My question is if the STM32MP2 have support for LibWebRTC as well?  Thank you for your reply

Evaluation of Display GRAM FunctionalityThe STM32MP157F-DK2 development board is equipped with an OTM8009A display.Link:Display panels hardware components - stm32mpuThis IC includes GRAM storage, which theoretically supports maintaining the display output even after the MPU enters sleep mode.Are there any available test results or evaluation conclusions regarding this?

According to the STM32MP257 datasheet:"1× USB 2.0/3.0 high-speed/SuperSpeed dual role data with embedded 480 Mbits/s and 5 Gbits/s PHY" "1× PCI Express with embedded 5 Gbits/s PHY (PHY shared with USB 3.0 SuperSpeed)"I would like to clarify:Can the USB3DR peripheral be used as a USB 3.0 SuperSpeed port while simultaneously supporting USB 2.0 High-Speed operation on the same connector? Is the embedded USB 2.0 PHY always available when the USB3DR interface is enabled? When PCIe is not used, can the USB3DR interface provide both the 480 Mbit/s USB 2.0 and 5 Gbit/s USB 3.0 links together as a standard USB 3.x port? Is the PHY sharing limitation only between PCIe and USB 3.0 SuperSpeed, or does it also affect USB 2.0 functionality?Any clarification on the USB/PCIe PHY sharing architecture would be appreciated.

Hello, I’m trying to initially build the Distribution-Package 6.2.0 (v26.02.18) as stated in the Wiki (https://wiki.st.com/stm32mpu/wiki/STM32MPU_Distribution_Package#Initializing_the_OpenEmbedded_build_environment)I am using a VM in Virtual Box running Ubuntu 24.04.5 LTS.I attached the log file.Any help is appreciated :)Thanks in advance.Ben

Hey, Guys!I’m designing an application to record TDM data source with 48k x 16 slots x 32Bit Format based on STM32MP151.But from the datasheet, there is some confusion.It seems the SAI supports 32bit and 16 slots from the SAI main feature description. But the FRL register is limited to 256, which cannot meet the requirement: 32*16 = 512 > 256.I’m using an external CODEC to generate the TDM clock, so STM32MP151 is in slave mode.Does anyone have experience with an application like this?Thanks!      Jampa.    

Hello ST team,I noticed what appears to be a documentation typo in the STM32MPU Wiki page “How to configure TSN switch”, section 3.1 – Run the PTP stack.The documentation states:“dePTP stack is started by default. To start it using via systemctl:”but the command shown immediately after that sentence is:systemctl stop deptpI believe the intended command is:systemctl start deptpThis is also consistent with the later “How to trace the PTP stack” section of the same page, where the documentation correctly uses:systemctl stop deptpto stop the service, and:systemctl start deptpto start it again.The Qbv section also states that gPTP synchronization should be started beforehand and thatdeptpis started by default.Could you please confirm and correct the command in section 3.1 if this is indeed a documentation typo?Thank you.

Greetings,I’m working on a STM32MP13X based development board as a learning project. One of the things I’m trying to achieve is a BIOS-like program stored in a NOR flash from which the MPU will boot from every time.After that, the program will load details of any relevant peripherals, Like size & configuration of the installed DDR3 memory & any bootable media like USB drive or SD card. After which the program will boot the bootable media (if any).The aim is to keep the system flexible like a general purpose computer, i.e. no fixed DTS configurations like DDR size, etc in U-Boot or Linux, So that any Linux distro with kernel support for STM32MP1 can be booted off the media.Is this possible? If so, then can you give me an overview of how this may be achieved? I understand this is alot of work which I am willing to do if someone can point me in the right direction.Regards,Aditya M.