STM32 MCUs Embedded software

HI.Previously, I successfully completed development for my project using the W25Q128 SPI Flash with its working External Loader file (.stldr).However, due to internal circumstances, we have recently replaced the external memory with the AT25SF128A. Since changing the chip, flashing code via the previous external loader no longer works.As a result, I need an External Loader tailored for the AT25SF128A.Could you please let me know if an External Loader for the AT25SF128A on the STM32H723 is already available from ST?If it is not available, could you provide guidance or reference materials on how to generate/modify an External Loader project for this specific memory?Thank you for your support.

My team is working on a project that is aimed to comply with IEC61508 SC 2 (SIL2).Our chosen MCU is the STM32H563VITx.My understanding is that utilization of HAL drivers when trying to meet IEC61508 is tricky and it is generally more common to write drivers from the ground up.However, I have seen in some scattered documentation that the STM32CubeH5 HAL functionality has been developed to a process compliant to IEC61508. Specifically the document UM3126 notes:“Within STM32CubeH5, both the HAL and LL APIs are production‑ready, checked with CodeSonar® static analysis tool, anddeveloped in compliance with MISRA C® guidelines, following a process certified according to IEC 61508 systematiccapability‑2 level (SC2). Reports are available on demand”I am unsure if this is correct given this is not documented in many places so would like clarity on the issue. If it is correct, does this mean that HAL functions generated from STM32CubeH5 can be used in a IEC61508 compliant system, and if so, how

I am working on an STM32N657 custom board. Previously, on the STM32N6570-DK, we were using the Octal SPI flash MX66UW1G45GXDI00. In our custom board, we have changed the external flash to the Quad SPI GD25LB256FWIGR. The Quad SPI configuration done. For firmware flashing, we are using STLINK-V3SET with STM32CubeProgrammer. Current Issue------------------ The STM32N657 target is detected properly in CubeProgrammer. I selected the external flash loader, firmware .bin file, and start address 0x70000000 & Appli address 0x70100000. However, when I click Start Programming, the erase operation fails and the target gets disconnected automatically. The CubeProgrammer log shows: Memory Programming ...File    : Camera_Dev_test_Appli-trusted.binSize    : 284.13 KBAddress : 0x70100000 Erasing memory corresponding to segment 0:Erasing external memory sectors [256 327]Error: failed to erase memoryWarning: Connection to device 0x486 is lostDisconnected from device. The ST-LINK connection itself is

Regarding the methods for reading data from the ADC injected group, I’ve only seen two approaches: interrupts and polling. Can I directly map memory in the software to ADCx->JDR1 to retrieve the data?  Just like：#define ADC_ADCRESULT0_ADDR ((volatile uint32_t*)&ADC1->JDR1)inline static const *uint32_t adc_buffer[0] = {ADC_ADCRESULT0_ADDR }

I have one question.The L451CC has 160K of SRAM split in 128K + 64K.According to the datasheet SRAM2 is rermapped just on top of SRAM1 giving a full block of 160K.Wonderful, but… not so wonderful because CubeIDE ignores the SRAM2 and restrict the memory space to SRAM1.Is there a way to use SRAM2 E.G. by writing a customized malloc like function (I did that for the L429 series and it works fine) ?static volatile void * ccm_current_pointer;static volatile uint32_t ccm_current_free_memory;static void ccm_Malloc_failed(void);// ADJUST ONLY THE RESERVED AREA SIZE// TO CHANGE THE CCM HEAP SIZE#define CCM_RESERVED_SIZE 0#define CCM_AS_HEAP_SIZE 65536 - CCM_RESERVED_SIZE#define CCM_AS_HEAP_BASE (0x10000000 + CCM_RESERVED_SIZE)void ccm_Heap_init(void){ ccm_current_pointer = (void *) CCM_AS_HEAP_BASE; ccm_current_free_memory = CCM_AS_HEAP_SIZE; memset((void *) ccm_current_pointer, 0, ccm_current_free_memory);}void * ccm_Malloc(uint32_t block_size, bool force_in_sram){ void * _ptr; uint32_t _

STM32N6: Black screen after HAL_NVIC_SystemReset() — FSBL not booting, works fine after NRST/power cycleGövde:Hello,I have a bootloader (FSBL) and a separate application on anSTM32N645L0, running from external XSPI NOR flash MX25UM25645GXDI00 in memory-mapped XIP mode (Octal DTR).Setup:FSBL configures the external flash into Octal DTR mode (volatile CR) at every boot and shows update/bootloader graphics on the display The application runs its own graphics To enter bootloader mode from the application, call HAL_NVIC_SystemReset()Problem:After HAL_NVIC_SystemReset(), the device stays on a black screen — the FSBL graphics never appear. However, if I reset via the NRST button or a full power cycle, everything boots normally.What I suspect:Since the N6 is flashless, BootROM must read the FSBL from external flash in standard SPI mode. My theory is that after a software reset the flash chip stays in Octal DTR mode (it doesn't lose power), so BootROM cannot read the FSBL at all.Questions:Is th

Hello,I implement kind of “lazy write cache” for flash and have problem.The consumer thread sends out cache write requests to the flash thread using events.The flash thread starts a SW timer which fires an event if no more cache write occurs.In the oscilloscope I see that the timer callback is run after timeout occured but the flash thread, which is triggered by the callback, is not executed immediately (it is run as soon as the next cache write event is received).I’m afraid this is a priority problem, but fiddling with task prios doesn’t help.Any idea is greatly appreciated!Thanks, Jochenuint32_t NCB_Cache_Write(eREQID_t eRid, ePNORNUM_t eFid, uint32_t ulOfs, uint8_t bData) { psNcbTaskArgs_t psArgs = &asNcbTaskArgs[eFid]; psArgs->pusBuf[ulOfs] = bData; psArgs->ulAdr = ulOfs; // run core thread after send request called by upper layer / send notification osEventFlagsSet(psArgs->phEventId, NCB_FLAG_FLUSH_REQ);}static void NCB_Timer_CB(void *arg) { // set TIMER event flag of

We need to use an ST67W611M1 on an STM32H5, running the Zephyr operating system in softAP mode. Currently, the Zephyr driver for the ST67W611M1 only supports STA mode. Is there a roadmap for this feature?Thanks,Denis M.

I am using the EEPROM emulation (X-CUBE-EEPROM) on a STM32C0.The default setting for number of variables is 100 : In eeprom_emul_conf.h : #define NB_OF_VARIABLES 100U /*!< Number of variables to handle in eeprom */If I understand this emulation correctly, it uses a number of 2K flash pages (minimum 2 for alternating...).Also, each (32bit) variable is stored as 8 bytes : 16bit virtual address, 32bit data, 16bit CRC.I understood there is also some header overhead of 32 bytes per 2K page.So the number of variables fitting in a single page is (2048 - 32) / 8 = 252So my question is then : why is the default value set to 100 io. 252 ???

I am trying to jump from bootloader to application at address 0x08004800 i STM32G070 but it crashes.The same code worked fine jumping to address  0x08007000Bootloader jump looks like this:#define BL_FLASH_START 0x08000000#define BL_FLASH_SIZE 0x4800 // 18 kB reserverade för BL, OBS! Startadress måste vara alignad mot 32 byte, dvs jämnt delbar med 32..#define BL_FLASH_END (BL_FLASH_START + BL_FLASH_SIZE-4) // 4 byte checksumma#define APP_FLASH_BANK_SIZE 0xDC00 // 55 kB / appl bank// Defines för applikationen#define FLASH_START (BL_FLASH_START + BL_FLASH_SIZE)....HW_WD_Trig();JumpAddress = *(uint32_t*) (FLASH_START + 4);Jump_To_Application = (pFunction) JumpAddress;// disable global interrupt__disable_irq();JumpAddress = *(uint32_t*) (FLASH_START + 4);Jump_To_Application = (pFunction) JumpAddress;/* Initialize user application's Stack Pointer */__set_MSP(*(uint32_t*) (FLASH_START));Jump_To_Application(); .ld for bor bootloader looks like:/* Entry Point */ENTRY(Reset_Handler)/* Highest ad

Hi all:I have a number of firmwares which use the older Standard Peripheral Library for STM32F4xx etc.I could switch to the new Low-Layer drivers, but I doubt it is worth the effort.I actually found the old Standard Peripheral Libraries quite all right. Unfortunately, STM is not maintaining them anymore, even in the face of obvious bugs like this one:Standard Peripheral Library limits STM32F4xx USART to 7.5 Mbit/s, instead of max 10.5 Mbit/shttps://community.st.com/stm32-mcus-products-25/standard-peripheral-library-limits-stm32f4xx-usart-to-7-5-mbit-s-instead-of-max-10-5-mbit-s-82037Are there any community forks of the Standard Peripheral Libraries I could switch to?Thanks in advance,  rdiez

Dear ST Community,We are working on a custom board using the STM32H747XG controller with a MIPI DSI display interface.Our display panel is RK055MHD091A0-CTG, with a resolution of 720 × 1280. The display uses the HX8394-F TFT driver IC, and we are using the 2-lane MIPI DSI interface: DSI Data Lane 0 DSI Data Lane 1 DSI Clock Lane We have configured the STM32H747 DSI Host in Video Mode and are using LTDC with an SDRAM framebuffer.The HX8394-F supports DBI Type C option 1, 3-wire serial bus to access command set under DSI I/F. The 3-wire serial bus is use: chip select line (CSX), serial input data (SDI),serial output data (SDO) and serial transfer clock line (SCL).According to the HX8394-F display driver requirements, the panel requires an initialization sequence with several commands for configuring parameters such as power, MIPI settings, gamma, GIP, etc., before starting the display.We would like guidance on the correct way to send these HX8394-F initialization commands from the ST

大家好！问题是这样的： 我正在尝试使用 STM32 ISP-IQTune 应用程序通过 STM32N657X0H3Q 板读取 PC 上的 IMX335 相机数据。但是，IQTune 无法检测到任何可用的 COM 端口。这是我的设置：硬件：板：STM32N657X0H3Q相机：IMX335（MB1854B模块，根据文档提供原生支持）。固件：已从 STM32N6 固件包中刷新 DCMIPP_ContinuousMode 示例。连接：已将板上的两个 USB 端口连接到 PC（USB-C 电缆）。开发板显示红色 LED 闪烁，表示程序正在运行。问题：尽管板子看起来正常工作，但 ISP-IQTune 显示“未检测到端口”。我已验证：USB 电缆支持数据传输（与其他设备一起测试）。已安装 STM32CubeIDE 驱动程序。IMX335 在 ISP-IQTune 文档中被列为兼容的传感器。问题：是否有其他步骤可以在 ISP-IQTune 中启用 COM 端口可见性？DCMIPP_ContinuousMode示例是否需要修改 ISP-IQTune 兼容性？应该只连接 CN18 （USB1），还是两个 USB 端口都需要？感谢您的时间和帮助！

Dear ST experts, I have configured UART (both RX and TX) in Normal DMA mode. I want to send a small data packet every 500 ms with using HAL_UART_Transmit_DMA (&huart, buffer, 10). But I noticed that only one shot is triggered. What is the problem? Should I do something in HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) callback? Best, Davood.

Hello St Teams, I have two MCUs (one as master and other as slave). They can send and receive data through UART (UART+DMA). The master/slave is always listening. Whenever, the slave receives command from the master, it sends data back to the master. The DMA is interrupted after receiving specified length of data in both MCUs. In the code, I check the first and the last byte to see everything works correctly. But the problem arises when I want to connect two MCUs via cable. At this time, the MCUs receive unwanted bytes due to glitching. How I can make the whole system robust to unwanted bytes when the data length is fixed? What strategy would you suggest? Best, Davood. 

I am encountering a memory access issue in my application, which runs on Azure RTOS on a custom STM32F767VIT6?based target board. The application receives JPEG images from an MQTT broker via the EC200U modem, using USART on the board. The problem arises when I declare a global array of size 180 KB to store the image. Even though I initialize this array with valid non?zero content (JPEG image data in hex), the debugger consistently shows all zeros when I attempt to read it. Interestingly, when I reduce the array size to 100 KB, the behavior is normal the data is correctly written and read. I am using the ST?Link 2.0 debugger from STMicroelectronics, and the project is built in STM32CubeIDE. Since my JPEG images can be as large as 180 KB, I need to resolve this memory limitation. Could you provide detailed guidance on the root cause of this issue and possible solutions? I have attached my workspace in .7z format for reference.

Hi, I am using an STM32F767ZI which is connected to a server via Ethernet. It is also connected to other STM32F767ZI devices that are part of the same system, and these devices communicate with each other over CAN. So far, everything is working correctly: the STM32F767ZI with Ethernet communicates with the server using TCP/IP and forwards the information to the other devices connected to the CAN bus. The problem is that I am now being asked to support firmware updates for all the devices connected to the CAN network, including the STM32F767ZI that has the Ethernet connection. I am not sure what the most optimal way to do this would be. I have also never programmed a bootloader before, although I think I should be able to do it. Is there a way to program all the STM32 devices connected to the CAN bus from a server that is connected to the system via an Ethernet cable? Should I change the design so that all devices are connected via Ethernet using TCP/IP and remove the CAN network altoge

Hello, I am working with this guide:How to integrate TouchGFX and camera middleware on an STM32N6570-DK  And was wondering if there was an easy way to capture snapshots instead of running the camera continuously.  I tried setting the mode to CMW_MODE_SNAPSHOT with no luck. I was able to get snapshot mode to work in the DCMIPP_SnapshotDecimationMode example, but it seems that example interacts with the ISP a little differently from the link above. The end goal is to store snapshots in different locations on PSRAM (multiple cameras muxed to the MCU's CSI port)

Hi, I want to use my F072's DACs to output a sin and cos signal. to save on memory I want to have only one buffer holding the values of a SIN function, COS values should be taken from the same buffer. Basically, I need the DMA for channel 1 to start from the beginning of the buffer and for channel 2 to start at an offset. Of course, I can't just do something like HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_1, lut, no_samples, DAC_ALIGN_12B_R);HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_2, lut + no_amples / 4, no_samples, DAC_ALIGN_12B_R);because that would make the dma access elements outside the buffer. in the reference manual I found the register DMA_CNDTRx register, is this the way to go? 

Hi all ,  Im facing a issue in TCP/IP - Ethernet using LWIP on STM32H723ZGT6 [NUCLEO - H723ZG] , that i gave completed ethernet configuration , ping is good , wrote a tcp_echoserver and modified with my desired outputs , everything was a woking upto a certain level, and i cant RX and Tx and fall into hard fault (Added a Video of the output). I'll add the code file as a zip.  Kindly help me to resolve ii. Thank You!!!.....

Hi, I am creating a project CubeMX that uses both Secure and NonSecure. I using USART1 for debugging, and my application only runs on SecureApp and cannot run NonSecureApp. I tried implementing the same as Template Isolation XIP but it still didn't work.

Hi, I have a question regarding the STM32N6 BootROM flash boot process. My understanding is that the BootROM loads the FSBL from an external XSPI flash device. However, it is not clear to me whether the BootROM: Uses a fixed XSPI/XSPIM configuration (for example, a specific XSPIM port), or Automatically probes and detects the flash location across available XSPI/XSPIM ports. For a custom STM32N6 board, the external NOR flash is connected through XSPIM Port1. I would like to understand whether the BootROM is capable of automatically discovering and booting from a flash connected to Port1, or whether Flash Boot is restricted to a specific XSPI/XSPIM port configuration. Could you please clarify: Does the STM32N6 BootROM scan multiple XSPI/XSPIM ports during Flash Boot? Is the boot source port fixed in ROM or configurable through OTP settings? If the flash is connected only to XSPIM Port1, can the BootROM still load the FSBL from it? Is there any documentation describ

This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.Hello,I am using a STM32L431 microcontroller. Bare-metal application in C using STM32CubeIDE and HAL library. I am trying to transmit an 8-byte CAN Message at 1Mbps baud rate every 1ms. The best I can do right now is successfully transmit one CAN message every 3ms (with every 13th or 14th message going out at 4ms interval.). Any transmission rate >3ms I do not have any issues. The system Clock is set to 80Mhz, using external 8Mhz crystal. Every 1ms (based on 500us timer), I add a CAN message to a queue (size 128). I check for any available TxMailbox and try to transmit using HAL_CAN_AddTxMessage. I also have a CANTransmit function that calls HAL_CAN_AddTxMessage in the HAL_CAN_TxMailboxEmptyCallback in case all 3 mailboxes were full. At present, there are no other devices trying to send any CAN messages on the bus expect the STM32 microcon

Hello Team, I want to connect a USB camera to an STM32H7 board. My STM32H7 supports USB OTG/Host. Is it possible to interface a USB camera with STM32H7? Does STM32H7 support USB Video Class (UVC), or is it better to use a DCMI parallel camera instead? Please suggest the required driver/middleware and recommended approach.   Thank You, Vijaya

Hello,I'm trying to write an application with TrustZone enabled that uses the LTDC peripheral.My application:boots into secure worldconfigures the LTDC peripheral and its interrupt, as well as the relevant GPIO pins, as non-secureswitches to the non-secure world.In the non-secure world, I configure the LTDC, passing a buffer placed in non-secure SRAM and start drawing. However, the screen stays black.I'm able to access the LTDC registers from the non-secure world, so it seems that the permission settings for the MCU are correct. My guess is that for some reason the LTDC peripheral itself does not have permission to access the SRAM, am I missing some other settings?