STM32 MCUs Embedded software

I am using the Analog Devices EVAL-ADE9430 Evaluation board for testing one of their devices. The Evaluation board uses the NUCLEO-144 STM32F413ZH processor. I am using the Keil uVision development setup to run and debug code.  I am specifically concentrating on the SPI Bus Driver and the timing. I have no previous experience with STM Devices and how the SPI transfers happen in the processor.   While walking through the code and following it on my scope to see the SPI Bus timing I am seeing something that does not make sense.  The AFERead32BitBuffer() function is called when you read a 32-bit register from the SPI Device which is an Analog Devices ADE9430 Chip (see Below).  The code calls HAL_SPI_Transmit() with the number of bytes it needs to transmit (see line 9 below). In this case it is transmitting a two byte command header where bits [15:04] are the register address and bits [3:0] is the R/W command, see example timing below.   When

Hello, I hope you are doing well.I am currently working on benchmarking the Ethernet communication interface on an STM32H753 Nucleo board.My setup involves sending data from a Python script to the STM32, where the data is encrypted, and then sent back. This allows me to measure the RTT and overall throughput.I initially used Mongoose, but I encountered several issues:With UDP, I cannot reliably send more than ~1500 bytes, since larger packets get fragmented or dropped.TCP works correctly, but the throughput varies significantly depending on payload size. For example:~2.7 MiB/s for 1400-byte payloads~7 MiB/s for 10240-byte payloadsI would like to know:What is the best networking stack or library for STM32 to achieve better performance and properly handle UDP large payloads?Given that Ethernet is 100 Mbps in my case, I am not reaching near-theoretical throughput even without encryption. Is this because I am measuring not only transmission time but also packet handling, buffering, and pro

Hello,I have been using the hrtim hardware on a prototype board with STM32G474RE and have noticed what might be a possible regression in CubeMX. Purpose:We are a group of students currently trying to develop FOC from scratch for controlling a BLDC-motor, this is a part of a bachelors thesis. As a part of developing the FOC we decided to use six-step commutation to start the motor before the FOC takes over. During the part of developing the commutation we have notice some strange behaviour between cubeMX versions.The problem:We are experiencing signal inversion with V6.17.0 of cubeMX with the exact same files pulled from the git repo. Either the migration fails for some reason or there is some sort of regression when it comes to the the configuration in CubeMX.6.16.1:HRTIM1 with slave-timers A,B,E are configured to output 6 PWM-signals with dead time configuration and complementary mode for CH2 of each timer.The output on the logic analyzer is as expected. It shows a duty cycle of

I am using the Analog Devices EVAL-ADE9430 Evaluation board for testing one of their devices. The Evaluation board uses the NUCLEO-144 STM32F413ZH processor. I am using the Keil uVision development setup to run and debug code.  I am specifically concentrating on the SPI Bus Driver and the timing. I have no previous experience with STM Devices and how the SPI transfers happen in the processor. so I apologize a head of time. The Analog Devices ADE9430 uses a a 16-bit CRC (CRC-16-CCITT) and from what I originally read  the STM32F413ZH processor supports 32-Bit CRC (CRC-32-CCITT).  Diving deeper into the NUCLEO-144 STM32F413ZH processor manual section "29.4.2 CRC calculation" indicates "The SPI offers CRC8 or CRC16 calculation depending on the data format selected through the DFF bit." When the DFF bit (SPI_CR1 bit 11) is 0 it uses CRC8, when the DFF bit is '1' it uses CRC16.https://www.st.com/resource/en/reference_manual/rm0430-s

I am having difficulties with initializing a SD Card.I am making use of the generated code to initialize the card:void MX_SDMMC1_SD_Init(void) I measured with a scope and I am getting 400KHz clock. All the pull-up resistors are correct and voltage is correct.Within the SD_PowerON() function, the function to send the MD8: SEND_IF_COND is called, but I get no response from the card. HAL Error Return is timeout.I tried a differ SD Card as well.Any suggestions where to start checking for potential issues?static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { __IO uint32_t count = 0U; uint32_t response = 0U; uint32_t validvoltage = 0U; uint32_t errorstate =0U; #if (USE_SD_TRANSCEIVER != 0U) uint32_t tickstart = HAL_GetTick(); #endif /* USE_SD_TRANSCEIVER */ /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ err

Hello everyone,I'm using the stm32G0 USB Host with firmware package V1.6.3.There is an issue with H2D control transfers, where the USB Host stack send a second OUT packet before sending an IN packet on the last packet.I wrote a usb dfu host class that uses USBH_CtlReq.From this picture on the left we can see the PC sending a DNLOAD packet to the stm32h7, first the OUT packet followed by an IN packet.On the right we can see the stm32G0 host sending an OUT packet followed by another OUT packet, before sending an IN packet. The device here is the stm32f4, which for some odd reason allows this (every single stm I tried allows this except h7, tested stm: F4, F7, G0, H5, L5). So my update actually works on every single stm except on the stm32h7.But in the middle picture, the host is still stm32G0, but the device is an stm32h7, which after receiving the second OUT packets NAK's it.From the picture, I would say that the stm32h7 is in the right here. It see that it got an OUT packet, which

Original post: https://community.st.com/t5/stm32-mcus-products/stm32h7-flash-crc/td-p/887279 Github: https://github.com/STMicroelectronics/stm32h7xx-hal-driver/blob/1501be883dae6f202c1d3f856ee6b11407dc257d/Src/stm32h7xx_hal_flash_ex.c#L733 HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result) { ... ... FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC; ... ... }​|= will not program the expected burst size if the reset value is not b00. It looks like on reset the value is b01 (16 flash words). So if user try to set to burst size of 4 flash words (b00) it'll remain set to b01.

I am running the Analog Devices EVAL-ADE9430 board and noticed if I enable CRC checking reading 32 bit registers fail while 16-bit registers always pass. I trace it down to the  AFERead16BitBuffer() function not returning a status after reading the register over the SPI bus. This allows 16 bit register reads to work all the time while 32 Bit registers fail all the time (that's another story).   See line 12 below:     HAL_SPI_Receive(&hSPI, (uint8_t *)&pData[0], 2 * numSamples, SPI_TIMEOUT); uint32_t AFERead16BitBuffer(uint16_t addr, uint16_t numSamples, uint16_t *pData) { int32_t status = SYS_STATUS_SUCCESS; cmdBuffer[0] = (addr >> 4); cmdBuffer[1] = ((addr & 0x0F) << 4) + 8; HAL_GPIO_WritePin(GPIOD, GPIO_PIN_14, GPIO_PIN_RESET); status = HAL_SPI_Transmit(&hSPI, (uint8_t *)&cmdBuffer, 2, SPI_TIMEOUT); if (status == 0) { HAL_SPI_Receive(&hSPI, (uint8_t *)&pData[0], 2 * numSamples, SPI_TIMEOUT); } HAL_GPI

 Hi everyone,I wanted to share a project I’ve been building over the last few years. It’s called Mk, an operating system built entirely from scratch for the STM32F746G-DISCO and STM32F746G-Eval2 boards.These boards are powered by an ARM Cortex-M7 running at 216MHz. Initially, my goal was just to implement a small scheduler, but I stacked layers one after another to make it as complete as possible. Currently, I think I've added enough layers to claim it as a functional, lightweight OS.Mk features:A KernelPreemptive, priority-based multitasking scheduler (fixed-priority, O(1) selection via hardware CLZ instruction) Trusted Execution Environment (TEE) using the Cortex-M7 MPU (privileged and unprivileged mode isolation) Synchronization primitives: mutex, semaphore, event flags, mailbox Fixed-size memory pools Synchronous and asynchronous callback execution systemA Dynamic ELF Loader Mk can load and execute external .elf binaries at runtime, relocated dynamically into 64 KB pages of the ext

Hello,   I am working on I3C private transfers. When I build the context buffer with HAL_I3C_CTRL_BuildTransferCtxPrivate I get an assert when IS_I3C_PRIVATE_MODE is checked against HAL_I3C_PRIVATE_WITH_ARB_RESTART. Is the exclusion of HAL_I3C_PRIVATE_WITH_ARB_RESTART from the macro below intentional? stm32c5xx_hal_i3c.c: line 574 #define IS_I3C_PRIVATE_MODE(MODE) (((MODE) == HAL_I3C_PRIVATE_WITH_ARB_STOP) \ || ((MODE) == HAL_I3C_PRIVATE_WITHOUT_ARB_RESTART) \ || ((MODE) == HAL_I3C_PRIVATE_WITHOUT_ARB_STOP) \ || ((MODE) == HAL_I2C_PRIVATE_WITH_ARB_RESTART) \ || ((MODE) == HAL_I2C_PRIVATE_WITH_ARB_STOP) \ || ((MODE) == HAL_I2C_PRIVATE_WITHOUT_ARB_RESTART) \ || ((MODE) == HAL_I2C_PRIVATE_WITHOUT_ARB_STOP))  Thank you, -Gil

Hello, I am looking for an example of how to use private I3C transfers for STM32C562RE. I read the I3C examples posted on Github but I did not find any controller or target examples that use HAL_I3C_CTRL_Transfer_DMA and HAL_I3C_TGT_Receive_DMA for private transfers using HAL2. Your help would be appreciated,Gil

Recently, I was trying to implement SDMMC+DMA+SDFAT to read and write the SD card of my Class on the STM32H750VBT6. Then I found that the DMA of SDMMC was gone. I saw some online materials saying that MDMA needs to be configured, and some also said that SDMMC does not need to configure DMA as it has its own independent IDMA bus. What is the actual situation when it is directly mounted on AHB? Are there any configuration screenshots and programs of CubeMX for SDMMC+DMA? I'd like to refer to it. Thank you!

Dear. AllI'm asking how to use STemWin on stm32h743 mcu.How to add STemWin on STM32CubeIDE? (Current Use Version. 1.13.0)?How can I run a project with the development board I bought? (STM32H743I-EVAL)?In particular, I want to run the STemWin_SampleDemo project.I`m use IAR EWARM ver 9.xx but in stm32cubeh7-v1-12-1 andSTM32Cube_FW_H7_V1.11.0\Repository\STM32Cube_FW_H7_V1.11.0\Projects\STM32H743I-EVAL\Demonstrations\STemWini find STemWin.ewp project which use OGLastSavedByProductVersion 8.20.2.14834.It mean`s STemWin.ewp should compile on EWARM 8.20 or late.Is it possible to use example on later version EWARM ?Best regards.

I'm using the latest library provided by the STM32Cube_FW_G0_V1.6.3, specifically STM32Cube_FW_G0_V1.6.3\Drivers\CMSIS\DSP\Lib\ARM\arm_cortexM0l_math.libbut when using IAR 9.20 I'm having the warning Warning[Lt009]: Inconsistent wchar_t size arm_sin_f32.o(arm_cortexM0l_math.lib) and 1 other objects in arm_cortexM0l_math.lib have wchar_t size 16 bits my_file.o and 54 other objects, some of them in rt6M_tl.a and 5 other libraries have wchar_t size 32 bits How do I avoid the mismatch?I would like to avoid to link the source code for the cortex M math library and compile it myself.

Hello, I have a device with a variable message stream in UART and there is the issue that I cannot know when it's stream ends due to gaps (so a single ReceiveIdle won't work). The device has clear framing via an interrupt so I use that.The final system will have limited DMA channels so keeping a ReceiveIdle always set is wasteful.As such there is the following workflow:HAL_GPIO_EXTI_Callback gets a signal there is a new message. That arms the DMA listener. On DMA callback, HAL_UART_Receive_IT is armed to catch possible remainder of message.On HAL_UART_Receive_IT it arms another DMA to get the rest of the stream (instead of doing a byte by byte interrupt, which is slow)We get another callback and stop the DMA/IT or we loop on IT and DMA.The issue is if this workflow is safe? Is there an issue arming DMAs on callbacks or IT on DMA callbacks?Thank you 

Title updated to better reflect the root problem; was originally 'Riverdi 12.1" + TouchGFX 4.25 + FATFS not working'Hi everyone,I am working on a Riverdi 12.1" display board based on STM32H7 with TouchGFX 4.25 generated project.Environment:TouchGFX 4.25STM32CubeMX generated projectSTM32CubeIDERiverdi 12.1" boardSTM32H7FreeRTOS enabledDebugging with ST-LINKProblem:BSP_SD_Init() returns MSD_ERROR_SD_NOT_PRESENT.In main.c:uint8_t res; res = BSP_SD_Init(); risultato = res; if(res != 2) { Error_Handler(); }The value stored in risultato is:MSD_ERROR_SD_NOT_PRESENTAdditional important behavior:When I start a FreeRTOS task that accesses FATFS/SD, the display becomes completely black and TouchGFX no longer shows images.This is my task:void StartDefaultTask(void *argument) { FIL file; UINT bw; for(;;) { SCB_CleanDCache(); SCB_InvalidateDCache(); if(BSP_SD_Init() == MSD_OK) { if(f_mount(&SDFatFS, SDPath, 1) == FR_OK) { if(f_open(&file, "log.txt", FA_OPEN_ALWAYS | FA_WRITE

Looking through the STM32Cube codebase, I’ve noticed a fairly strange but thoroughly consistent coding style. Indentation size is 2 spaces, using space for indentation; bracing style is more similar to Allman’s style rather than K&R and 1TBS. Naming style is also uniform, using CamelCase for external identifiers such as functions, structure fields, and global variables; along with a bit of Hungarian notation here and there (for example, pTxBuffPtr).This style is mechanically consistent through STM32Cube firmwares, drivers (LL, HAL, and CMSIS), code generated by STM32CubeMX, and BSP drivers. Even example projects follow suit.Could STM employees please share with us some documentation or guideline regarding this coding style? Looking for something similar to the Linux Kernel Coding Style and the Google C++ Style Guide. Configurations for formatter tools such as clang-format would also be appreciated.

I am working on converting projects from STM32F745VET to STM32U575VGT. Part of the startup routine of the projects is checking for flash errors using the CRC peripheral. The STM32F7 projects initialize a DMA channel in the following way: void MX_DMA_Init(void) { /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); __HAL_RCC_DMA2_CLK_ENABLE(); /* Configure DMA request hdma_memtomem_dma2_stream1 on DMA2_Stream1 */ hdma_memtomem_dma2_stream1.Instance = DMA2_Stream1; hdma_memtomem_dma2_stream1.Init.Channel = DMA_CHANNEL_0; hdma_memtomem_dma2_stream1.Init.Direction = DMA_MEMORY_TO_MEMORY; hdma_memtomem_dma2_stream1.Init.PeriphInc = DMA_PINC_ENABLE; hdma_memtomem_dma2_stream1.Init.MemInc = DMA_MINC_DISABLE; hdma_memtomem_dma2_stream1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; hdma_memtomem_dma2_stream1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; hdma_memtomem_dma2_stream1.Init.Mode = DMA_NORMAL; hdma_memtomem_dma2_stream1.Init.Priority = DMA_PRIORITY_LOW; hdma_memtomem_dma2

Hello,I’m working on an STM32H757 (Cortex-M7 core, dual-core system) using SDMMC1 + FATFS (CubeMX-generated stack) and I consistently hit a blocking issue: Core issuef_mount() always returns:FR_NOT_READYor the execution breaks inside Error_Handler() depending on build/debug timing. Hardware / system contextMCU: STM32H757 (Cortex-M7, DCache enabled)SD interface: SDMMC1, 4-bit modeDMA: enabled (CubeMX SDMMC DMA configuration)External subsystem: Riverdi TFT display 12.1 inches (LTDC active)FATFS: CubeMX middleware (generic SD diskio template)No RTOS Software architectureSTM32CubeIDE latestHAL SDMMC driver (CubeMX generated)FATFS with sd_diskio.c DMA templateBSP layer present (mixed HAL/BSP abstraction)Cache enabled (I/D Cache ON, MPU default CubeMX config)Observed behaviorDuring initialization:BSP_SD_Init() returns OKSD card is physically detectedHAL_SD_GetCardState() does NOT consistently reach SD_TRANSFER_OKSD_CheckStatusWithTimeout() frequently times outFATFS layer repor

Follow-on from STM32F030K6T6 microcontroller with Adafruit 2478 display and touchscreen.Hello all, i have a part of code for the touch screen for the 2478 display.I have found an example made with Arduino and i have adapted It for stm32, i would like to know if my code Is fine or It has some issues to fix and what u would suggest me to do. This part Is only for the touch controller of the display but i got several questions, like how many readings i should make from the ADC? rn i do and average basically.  #include "main.h" #include <stdint.h> /* ================= CONFIGURAZIONE ================= */ #define LCD_W 320 #define LCD_H 240 // PIN TOUCH (MODIFICA!) #define X1_PORT GPIOA #define X1_PIN GPIO_PIN_0 #define X2_PORT GPIOA #define X2_PIN GPIO_PIN_1 #define Y1_PORT GPIOA #define Y1_PIN GPIO_PIN_2 #define Y2_PORT GPIOA #define Y2_PIN GPIO_PIN_3 // CANALI ADC (MODIFICA!) #define ADC_CH_Y1 ADC_CHANNEL_2 #define ADC_CH_X1 ADC_CHANNEL_0 #define ADC_SAMPLES

Hi, I am currently implementing an HTTPS server using mbedTLS 3.6.5 and LwIP on an STM32H7S7L8 platform running FreeRTOS.Our mbedTLS configuration  are fully functional, as we already have a stable, working TLS implementation on an MQTT client using the same stack.However, we are encountering an issue during the TLS Handshake phase on the server side after configuring the client sockets to non-blocking mode (O_NONBLOCK). While the listening socket correctly accepts incoming connections, the handshake loop fails.I have attached the relevant snippet of our server thread implementation, including our I/O callbacks.Could you please review our non-blocking I/O logic and handshake loop to see if we missed a specific configuration requirement or state handling for mbedTLS 3.x in server mode?  /* STM32CubeMX Specific Parameters (not defined in opt.h) ---------------------*/ /* Parameters set in STM32CubeMX LwIP Configuration GUI -*/ /*----- WITH_RTOS enabled (Since FREERTOS

I am using the Analog Devices EVAL-ADE9430 Evaluation board for testing one of their devices. The Evaluation board uses the NUCLEO-144 STM32F413ZH processor. I am using the Keil uVision development setup to run and debug code.  I am specifically concentrating on the SPI Bus Driver and the timing. I have no previous experience with STM Devices and how the SPI transfers happen in the processor. so I apologize a head of time.  My question is very basic I am trying to understand how the NUCLEO-144 STM32F413ZH board is transmitting the data over the SPI Bus. What setup is involved and what kicks off the actual transmission in the the HAL_SPI_Transmit() code below. The code i am using is transmitting 8 bits at a time.  The Chip Enable (SS) is set active prior to this code. I see a structure called hspi that has a bunch of parameters that are initialized at line 29 below By single stepping know when line 108 below executes I can see 8 bits of data on my scope. I

Hello, I am working on a project using DMA and UART HD to communicate between multiple MCUs.  I have an issue where when one MCU starts up, it momentarily interrupts the UART HD bus and sometimes causes a UART and/or DMA error.Since I am using the STM32CubeMX packages for the HAL libraries, I tried to recover from the issue by several means, but I noticed there seems to be no provided method in the stm32h5xx_hal to recover once hdmarx->State = HAL_DMA_STATE_ERROR.  Calling any of the UART or DMA abort functions (HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_DMAStop()) does not reset the DMA State.  The call chain for HAL_UART_Receive_DMA() eventually checks the DMA State and just returns an error.I have found 2 methods that manage to work around the issue, but I am not satisfied with them because they are not at all elegant:Method 1: Call HAL_DMA_DeInit(), reset the Parent pointer back to huart, then call HAL_DMA_Init().  I feel like it might be missin

Hello all, I've been having trouble with the ADC system on the STM32G071G8U6.  I'm using the STM32CubeMX to generate initialization code.  I have 5 external A/D inputs and it appears I am not getting readings anywhere near the real values, so I have switched to trying to just read the internal reference.  I hope that if I can get the internal reference or the temperature to read correctly, I'll be able to solve the problems with the external inputs. My VDD is provided from a 2.5 volt LDO.  Looking at it with a DVOM, that looks accurate. I am running the A/D at 12 bit resolution and my clcok prescaler is Synchronous clock mode divided by 2.  I have the sampling time set to the maximum available in Cube, 160.5 cycles. I have a polling routine running every 1 second that reads all 5 external and all 3 internal channels. I set the VREFEN and TSEN bits in the ADC CCR register at the end of init and leave them enabled. I realize there may be board related problems wi

This is some feedback for the STM32C5 OEMiRoT example provided by ST.This is based on the STM32C5-MCU-HAL2.0.0 pack download 06-05-2026.Attached you can also find the CMake Config files for the example, specifically for the NUCLEO-C542RC board.General Bug Provisioning Python ScriptThe provisioning python script has a small bug when it comes to the prebuild script which adjusts the linker files.These files are compiler specific so the correct adjustment function needs to be called.This compiler dependent code is missing in the `_update_linker_define()` function in `STM32C5-MCU-HAL/rot/rot_provisioning/helper/project/project_generic.py` starting at line 318:linker_path = self.config.get_compiler_linker(compiler) value = f"0x{self.flash_layout.get_flash_layout(define):X}" update_define_in_file(linker_path, define, value)change tolinker_path = self.config.get_compiler_linker(compiler) value = f"0x{self.flash_layout.get_flash_layout(define):X}" if (compiler == "gcc"): update_variable_