STM32 MCUs

HI，   I am using stm32wba65i_dk1 board to develop my ble audio application.  I choose zephyr as my software platform and tmap as ble audio profile. However, when the TMAP application initiates advertising, the Pixel 9 cannot detect the device name broadcast by the TMAP peripheral. I also captured over-the-air packets using the professional BLE sniffer X240, which confirmed that no BLE advertising packets were transmitted from the STM32WBA65I_DK1 board.I enabled logging for all HCI commands sent by the HCI Core and all received HCI events, yet no obvious anomalies were observed in the HCI logs. I am unable to identify the root cause of this issue. # 1. LE Set Extended Advertising Parameters [v1]Send Command:[00:00:03.106,000] <dbg> bt_hci_core: bt_hci_cmd_send_sync: buf 0x20010c18 opcode 0x2036 len 25[00:00:03.110,000] <dbg> bt_hci_core: bt_hci_cmd_send_sync: cmd params 00 01 00 20 00 00 30 00 00 07 01 00 00 00 00 00

Hi,STM32H533 datasheet (DS14539 Rev 2) in table 88 says that RDY input setup and hold time are both 0.5ns. From my naive point of view it looks like superb value (RDY have to be stable only +-0.5ns around CLK edge). Isn't that a typo ? (STM32H7 PSSIs hold time is about 5.5ns)Thanks,Michal Dudka

 I have activated spread spectrum on two of the three PLLs I’m using in an STM32H7S7 via codeLL_PLL_SpreadSpectrumTypeDef sspr2;LL_PLL_SpreadSpectrumTypeDef sspr3;// in SystemClock_Config LL_RCC_PLL2_EnableSpreadSpectrum(); LL_RCC_PLL3_EnableSpreadSpectrum(); sspr2.DitheringRPDFN = 1; sspr2.DitheringTPDFN = 0; sspr2.IncrementStep = 1200; sspr2.ModulationPeriod = 10; sspr2.SpreadMode = LL_RCC_PLL_SPREAD_CENTER; LL_RCC_PLL2_ConfigSpreadSpectrum(&sspr2); sspr3.DitheringRPDFN = 0; sspr3.DitheringTPDFN = 0; sspr3.IncrementStep = 214; sspr3.ModulationPeriod = 60; sspr3.SpreadMode = LL_RCC_PLL_SPREAD_CENTER; LL_RCC_PLL3_ConfigSpreadSpectrum(&sspr3);Is there a way in CubeMX to activate it to make the settings generated automatically, as everything else I’m using?I’ve checked the RCC section in System Core as well as the Clock Configuration tab, but I can’t see anything regarding spread spectrum

Hello everyone,I am facing a flashing/debugging issue with the STEVAL-SPIN3202 Rev 3.1 board.Board:STEVAL-SPIN3202 Rev 3.1Software Used:STM32CubeIDESTM32CubeProgrammerProblem:While trying to flash or debug the board from STM32CubeIDE, I get the following error:"Failed to start GDB server""Error in initializing ST-LINK device""Failed to connect to device"Also, in STM32CubeProgrammer:Read data operation failsTarget connection sometimes not detectedAdditional Observations:ST-LINK USB is detected intermittentlyBoard LED becomes dim/slow ON sometimesReinstalled STM32CubeIDE and driversInstalled ST-LINK driversTried different USB cables and USB portsTried lower SWD frequencyTried Hot Plug modeTried BOOT0 methodStill unable to flash or read targetI would appreciate guidance on:Correct jumper settings for STEVAL-SPIN3202 Rev 3.1Whether onboard ST-LINK firmware may be corruptedPossible hardware protection/reset issueCorrect power supply requirements during flashingThank you.

Hi everyone,Regarding bits [31:16] of the TAFCR register in the STM32H723 RTC, I found that the RM and SVD description files don't match. Could you please tell me if the RM register description or the SVD description file is incorrect?The differences are shown in the following figure: 

We are using the EVSPIN32F06Q1S1 board and have configured TIM1 PWM outputs as CH1/CH1N → PA8/PA7, CH2/CH2N → PA9/PB0, and CH3/CH3N → PA10/PB1. While probing the board, we observed PWM waveforms at test points TP1, TP2, and TP3, which according to the documentation are connected to RES1, RES2, and RES3 rather than to PA8, PA9, and PA10. The complementary outputs are also present and behaving as expected at their respective MCU pins. Could you please clarify how the TIM1 PWM signals are being routed to TP1–TP3 and whether RES1–RES3 are internally connected to the TIM1 outputs on this board?

hello guys i hope you’re doing good,I have a problem while using a Nucleo board STM32F446 with the IHM08M1 driver and a BLDC motor.The issue is that I'm trying to use MATLAB to configure it, and it didn't work. I don't know if the gate driver is necessary to make it work, or maybe the logic (the logic to configure or run the BLDC motor) is not correct. Please, do you have any idea to help us? Can someone tell us how to make it work? i'm really stuck

Hello, I wrote a code to erase BANK2 flash memory for STM32G0C1VET6. The thing is that in some cases the erasing part works but in some cases it fails.I wrote the code to be ran in BANK1,the production code will use the proper start address and size, for this testing I’m forcing the erasing to happen in BANK2 for pages 0 and 1. As I commented, in some cases the erasing works, but sometimes there is an error returned by HAL_FLASHEx_Erase, which is HAL_TIMEOUT. I added proper refresh to watchdog and also some PREFETCH calls but even with that the issue persist. Attached is an image of the SR register once the HAL_TIMEOUT is returned. If I continue the execution of the code there is a hard fault caused when calling the HAL_FLASH_Lock (image attached). What could be wrong?I'm using STM32CubeIDE along with Stlink - V3.If the flash is already erased, calling the Erase function could cause the problem?Could it be related to some FLASH latency configurations?bool __attribute__((optimize("O0"))

UART independently working fine but with CAN, it is not working. Even simple welcome msg also no coming over UART . Even when I comment CAN init, issue is there. The error has been conveyed by a member earlier also. Any resolution provided by ST?

This is really a minor one. More an inconvenience than an actual problem. But it would be nice to get it solved, and to gain some understanding of what actually happens.I have a few different applications for various STM32 families, with a homemade bootloader added to it. The bootloaders are placed from address 0x08000000, and the applications begin at a higher address. Typically 0x08010000. The bootloaders and applications run fine. Bootloaders can start the applications, and applications can invoke the bootloaders. No problem there.The only issue I have is when uploading a new application from STM32CubeProgrammer, through the ST-LINK V3. I typically do this when debugging. But when I do it, even if the “Run after programming” checkbox is checked, the microcontroller isn’t started correctly after upload. When I debug this issue, the microcontroller seems to be stuck in an endless loop in the application. (Not the bootloader.)In the code I’m currently working on, this is the place wher

I have followed the instructions in GIT  to make ethernet works correctly on STM32H750 (setup TX/RX descriptors and their MPU config, also the LWIP heap and its MPU config, and the RX buffers).Everything seems working correctly after hours of setup and debugging, but the thing that break Ethernet and make it not working is when handling the unicast UDP or the UDP IO stream of OpEner it trigger a BUS Error in MAC DMA and stop everything from working, the explicit communication based on TCP works correctly and doesn’t break the Ethernet.I debugged for days of what could generate a bus fault error, then i find the udp when uses netconn it doesn’t copy the prepared buffer on lwip heap for sendig and in other way it give it directly the address of udp payload from the task stack, and this trigger a Bus Error when calling HAL_ETH_Transmit_IT because the task stack is not DMA accessible.So I made a workarround in low_level_output to detect the payload from outside lwip heap and copy that payl

Hello:Observation (empirical, multiple boundaries confirmed):When placing DMA linked list nodes (36 bytes each = 9 words) sequentially in SRAM1,if a single node spans certain addresses, the GPDMA channel enters DTEF statewhen fetching that node. Confirmed problematic boundaries in SRAM1 (192KB, 0x20000000 - 0x2002FFFF):- 0x20010000 : crossing FAILS- 0x20020000 : crossing FAILS Both boundaries appear at 64KB intervals within SRAM1, which suggeststhat SRAM1 may be internally organized as multiple 64KB blocks/banks. Test cases:Test 1: Node array starting at 0x20011A54 (natural placement)- Nodes 1-1633: within bank containing 0x20010000-0x2001FFFF → OK- Node 1634: spans 0x2001FFF8 - 0x2002001C → FAILS (crosses 0x20020000) Test 2: Node array starting at (0x20010000 - 44)- The first node spans 0x2000FFD4 - 0x2000FFF8 (OK)- The second node spans 0x2000FFF8 - 0x2001001C → FAILS (crosses 0x20010000) Test 3: Node array starting at (0x20010000 - 36)- The first node ends exactly at 0x20010000- No

Device Under Test: PXN V9 Gen2 Steering Wheel (operating in native D-Input mode) Hardware Platform: STM32F446RE Nucleo Board acting as a USB Host. Toolchain: STM32CubeIDE. Driver Framework: Custom embedded USB Host HID stack implemented by extending and adapting the native usbh_hid.c library provided by the STM32Cube firmware package. Analysis Tools: Wireshark with a USBPcap I am attempting to initialize a force feedback (rumble) effect sequence from the STM32 host. According to the USB PID specification, the transaction sequence rules: Send Create New Effect Report (Report ID 0x05) via a Control Out transfer. Read PID Block Load Report (Report ID 0x06) via a Control In transfer to retrieve the allocated Effect Block Index. The Symptom: When performing the Control In transfer to fetch Report ID 0x06, the data payload returned to the STM32 memory buffer is entirely filled with 0x00 bytes instead of a valid allocation status or a non-zero block index handle. No asynchronous data

Hi guys, I’m using lwip libray with netconn api on stm32h7, I want to enable the receive timeout using netconn_set_recvtimeout method. In order to do that LWIP_SO_RECVTIMEO macro should be set to 1 (default value is 0). There is no LWIP_SO_RECVTIMEO macro in the LWIP section of the .ioc file.How can I configure it ? Shoudl I set another macro in the .ioc or should I change LWIP_SO_RECVTIMEO value in the header file ? 

Hi, I’m looking into the WL55JC1 for a project which would require the system to remain dormant (ideally standby) for weeks, maybe months and then resume operation on a set date at a set time. I would like to use LSI as power and space will be very limited.So far I’ve discovered, that of course there is an RTC and it has alarms that can be used to wake from standby mode. However all examples and documentation I can find only ever use times or maybe day-of-week or day-of-month as the set wake up time. Never a full date and time. Looking at the code, stm32wlxx_hal_rtc.h defines a struct RTC_AlarmTypeDef with fields for seconds, minutes, hours and either a day-of-month, or day-of-week.Is it really not possible to give the system a full a date and time yyyy-mm-dd and hh-mm to wake up at? Will I need to build workaround waking up at least once a month to recalculate the next wake-up until the actual target time is within the same calendar month?Or am I overlooking something?I’d appreciate a

custom board, The USB D+ and D− lines are connected directly from the MCU to the USB Type-B connector, with no intermediate components. There is no pull-up resistor on the D+ line, as I understand that the MCU provides the pull-up internallyAs far as I know, the stm32u595 supports USB High-Speed using its internal PHY.CubeMX Version: 6.18.0Reference project:https://github.com/STMicroelectronics/STM32CubeU5/tree/main/Projects/STM32U5G9J-DK2/Applications/USBX/Ux_Device_CDC_ACMI configured my .ioc file to match the reference project as closely as possible. UART is not used.Issue:I implemented a simple CDC ACM echo function to verify USB communication.In Full-Speed (FS) mode, the echo function works correctly. The PC recognizes the device, and both transmit and receive operate normally. In High-Speed (HS) mode, however, the PC does not recognize the USB device at all (it reports an unknown or unrecognized USB device), so communication cannot be established.What could I be missing, or what

Hello,I dont understand in the AN4776, page 66 the following: /****** Master mode configuration: Trigger update mode *******/ /* Trigger of TIM2 Update into TIM1 Slave */TIM1->CR2 &= ~ TIM_CR2_MMS;TIM2->CR2 |= TIM_TRGO_UPDATE; why TIM1? there should have to mask the TIM2 master settings, before setting TRGO update, or i mistake? Moreover the TIM1 have been already set and active.

I'm trying to disconnect a ethernet cable after flashing a code Then I'm getting [00:01:50.522,000] <err> net_tcp: net_send_data()[00:01:52.200,000] <wrn> net_if: iface 1 is down[00:01:52.200,000] <err> net_tcp: net_send_data()[00:01:52.480,000] <wrn> net_if: iface 1 is down[00:01:52.480,000] <err> net_tcp: net_send_data()[00:01:52.900,000] <wrn> net_if: iface 1 is down[00:01:52.900,000] <err> net_tcp: net_send_data()[00:01:53.530,000] <wrn> net_if: iface 1 is down[00:01:53.530,000] <err> net_tcp: net_send_data()[00:01:54.475,000] <wrn> net_if: iface 1 is downThis is expected since trying to connect it backWhen I reconnect ethernet cable Im getting an below error [00:01:54.475,000] <wrn> net_if: iface 1 is down[00:01:54.475,000] <err> net_tcp: net_send_data()[00:01:55.282,000] <inf> phy_mii: PHY (0) Link speed 100 Mb, full duplex[00:01:56.212,000] <err> os: ***** USAGE FAULT *****[00

Hi ST Team,I am trying to enable Bluetooth LE Privacy (Resolvable Private Address) on an STM32WB55CG.EnvironmentMCU: STM32WB55CG STM32CubeWB Package: v1.23.0 BLE Stack: v1.23.0.3 FUS: v1.2.0.0What I changedI changed the address type from: #define CFG_BLE_ADDRESS_TYPE PUBLIC_ADDRto #define CFG_BLE_ADDRESS_TYPE RESOLVABLE_PRIVATE_ADDRThe generated code calls: aci_gap_init( role, 2, ...);and aci_gap_set_discoverable( ... RESOLVABLE_PRIVATE_ADDR, ...);Initially, aci_gap_set_authentication_requirement() was also using CFG_BLE_ADDRESS_TYPE as the Identity Address Type. I found an ST forum discussion mentioning this is incorrect, so I changed it to: aci_gap_set_authentication_requirement( ... PUBLIC_ADDR);However, the behavior did not change.Observed behaviorWith CFG_BLE_ADDRESS_TYPE = PUBLIC_ADDRPairing succeeds. Device works normally.With CFG_BLE_ADDRESS_TYPE = RESOLVABLE_PRIVATE_ADDRConnection is established. Pairing fails. ACI_GAP_PAIRING_COMPLETE_VSEVT_CODE

Dear team, hello, I've drawn a power supply circuit diagram for the STM32F051R8T6 but I'm a little hesitant. The diagram of my circuit is below. Have I done it correctly? Thank you for your answer. 

Hello, I have an STM32H573 project with TrustZone enabled. After the CPU goes into non-secure mode and during execution of the HAL_Init() function (more specifics below) a hard fault occurs. There is only a hard fault during the execution from a non-secure state. In the secure state (at boot) the HAL_Init() function successfully runs. Is there a configuration for the RCC not enabled by default that I a missing, allowing it to be accessed by both Secure and Non-Secure CPU states?Within GTZC_S TZSC - Privilegeable peripherals I cannot enable it. I see no relevant settings (I have tested a few that might be loosely related but no solved) in RCC. In the code below I have used an arrow (<--) to denote exactly where the hard fault occurs (Verified with debugger)Non-Secure Entry Code (CubeMX Generated):int main(void){ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* MPU Configuration-------------------------

Hello, I may be missing something, I cant generate the SPI_init() method within main() (also pins are yellow ?)…I have generated;  HAL_Init(); /* Configure the system clock */ SystemClock_Config(); /* Initialize all configured peripherals */ MX_GPIO_Init(); Cheers

Hello,I have completed this guide successfully:How to integrate TouchGFX and camera middleware on an STM32N6570-DK However, I am running into an issue when I try to add SDMMC2 or ETH in the .ioc.  After I generate code then build in the IDE, I get the below error: C://TouchGFXProjects/VisionControlboard2/FSBL/Core/Src/main.c:334:(.text.startup.main+0x12c): undefined reference to `HAL_SD_Init'C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/bin/ld.exe: (HAL_SD_Init): Unknown destination type (ARM/Thumb) in ./Application/User/Core/main.oC://TouchGFXProjects/VisionControlboard2/FSBL/Core/Src/main.c:334:(.text.startup.main+0x12c): dangerous relocation: unsupported relocationProject in link below:https://app.box.com/s/bdbyzi5eqvqhgib90klxgehmhs8pkynsWhat is the best method to get this resolved?  I am using STM32CubeIDE Version 2.1.1

Hi,I would like to ask whether support for the STM32C5 family is planned in the STM32 Motor Control SDK (MC-SDK).If so, could you please provide an indication of the expected release timeframe or roadmap for its integration?We are currently evaluating STM32 devices for a motor control application and would like to understand whether STM32C5 family will be officially supported by the MC-SDK in the near future.Thank you in advance for your support.Best Regards

Hi,we have a question regarding the Secure Manager Internal Trusted Storage size on the STM32H73 series.We have configured the following options:external flash profile 0 secure modules (=SMAK_0 ?)According to UM3254 it is our understanding the ITS size can now be up to 56 Kbyte:Our application project.py prebuild seems to extract value “9”, which means 9 * 8 Kbyte (Flash sector size) = 72 Kbyte? Jul  8 13:27:10 2026 : [INF] Searching the parameter with <Name>ITS size</Name> element2026-07-08 13:27:10,542 - DEBUG - Wed Jul  8 13:27:10 2026 : [INF] Parameter found. Verifying information of '<Value>0x9</Value>'2026-07-08 13:27:10,543 - DEBUG - Wed Jul  8 13:27:10 2026 : [INF] The modification is not necessary2026-07-08 13:27:10,543 - DEBUG - Wed Jul  8 13:27:10 2026 : [INF] The tag <Value> has already the correct content (0x9) Is there a misunderstanding on our end about the profile, memory configuration, UM3254 table, the prebuild proccess or the conversion