Unable to Get RMII Link on KSZ8863RLL Port 3 (STM32F746)

[SeppeBudenaers]

I am developing a device based on an STM32F746VET6 with two Ethernet ports. To implement this, I chose the KSZ8863RLL, as it provides two external Ethernet PHY ports and an RMII interface to the STM32.

At the moment, Port 1 and Port 2 are both working correctly at 100 Mbps full duplex. I can successfully transmit and receive data through both ports. However, I cannot get Port 3 (the RMII CPU port) to establish a link.

I'm a bit confused about the correct RMII interface connections. I am using Clock Mode 5, and my understanding is that the external 25 MHz crystal is internally multiplied to 50 MHz, with REFCLKO_3 providing the 50 MHz reference clock to the STM32. Is that interpretation correct?

This is how I originally routed the RMII signals:
 

After reading through the datasheet and application notes, I also came across the following information:

Based on that, I bodged my PCB to match the recommended connections, but I still cannot get a link on Port 3.

Has anyone successfully used the KSZ8863RLL in RMII Mode 5 with an STM32? Am I misunderstanding how the RMII interface or clocking should be connected, or is there something obvious I'm missing?

Original schematics of the PCB are attached bellow
 

 

[SeppeBudenaers]

The last table is a interpretation of 6-1 page 7 of this document https://ww1.microchip.com/downloads/en/DeviceDoc/KSZ8863RLL-Hardware-Design-Checklist-00003048A.pdf

to my understanding the KSZ8863RL is standard in PHY MAC mode and that is also what is needed for communicating with the STM.

[mƎALLEm]

See also:

ETH: anybody used KSZ8863RLL?

Custom PCB, STM32H7 and KSZ8863RLL, RMII

Users in these posts may help you.

[SeppeBudenaers]

Hi I have read these but they don't show the connection towards the MCU, and are closed for discussion so i cannot ask them how they solved it. 

[mƎALLEm]

You can mark them in this thread using @

[LCE]

Here’s my pin connections with a H733.

The port names are the names used by the STM32.

 

I only got it working by setting the PHY clock to internal, by setting register 198 (0xC6) / bit 3 via I2C (SPI is also an option I think - but the “advanced control” registers are not accessible via MDIO / MII management).

You also have to take care with the registers how and which port you set / check.

[SeppeBudenaers]

Hi, sorry for the late response.

Thank you for sharing the schematics so I could cross-check our design. I managed to get my implementation working. The issue turned out to be a software incompatibility between the CycloneTCP driver and my STM code.

I am now configuring everything manually, including the network settings, and I also manually send and poll for UDP packets. This approach seems to be working reliably for me.

Thanks again for your help!