STM32N6 FMC SDRAM: what does "Primary interfaces used" mean, and which pins are the primary ones? Hello, We are designing a board with STM32N647X0H3Q (VFBGA264) and a 16-bit SDR SDRAM (512 Mbit, x16, 3.3 V LVTTL) on the FMC, and we would like to run SDCLK at 133 MHz and 166 MHz. In DS14791 Rev 10, section "SDRAM waveforms and timings", the text says: "In all timing tables, Tfmc_ker_ck is the fmc_ker_ck clock period, with primary interfaces and RETIME = 1: - Maximum FMC_CLK = 166 MHz at 20 pF for 2.7 V < VDD < 3.6 V Otherwise: - Maximum FMC_CLK = 75 MHz at 20 pF for 2.7 V < VDD < 3.6 V" and Tables 86 to 89 have note 2: "Primary interfaces used." However, I could not find a definition of "primary interfaces" anywhere in DS14791, RM0486, AN5967 or ES0620, and the CubeMX device database shows no difference between the alternative pins of the same FMC signal. On VFBGA264, the control, address, SDCLK and NBL signals each have only one pin, but every data line has two or three possible pins (all AF12), for example: Signal Option 1 Option
