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I’ve started a thread before the migration. Now as it received the best answer, I would like to close it by marking that answer, but I can’t as the appropriate item is missing from the posts’ menu.To exclude some potential issue with this incarnation of the forum: can Moderators please confirm that this is consequence of the migration, or is it something else?JW

Could you please clarify whether the ST67W611M1 supports IEEE 802.11k/v/r and Wi-Fi roaming?If it does, could you please point me to the documentation that describes this support? I could not find any information about it in the datasheet, user manual, or ST Wiki.

ETH is obviously a dual-clock peripheral, and some of the registers are most probably behind a synchronizer, in the MII clock domain. It’s not unlikely that reading some of those registers imposes waitstates. Writing may not, but then those are subject to the Successive write operations to the same register might not be fully taken into account erratum (which hints at the fact that there’s a 4-MII-clock synchronization mechanism, at least for writing).Can ST confirm or deny, whether reading and/or writing ETH registers imposes waitstates, and in case of yes, can ST please list related registers and also quantify number of waitstates. Here’s why.In particular, we need this to be quantified for the ‘F4xx, but for other families it would be a bonus to have this, too.Thanks,JW

Hello,I am a Master's student comparing FreeRTOS and Zephyr on the Cortex-M33 of the STM32MP257F-DK, with Linux running on the Cortex-A35. I measure task timing on the M33 with the DWT cycle counter and an oscilloscope, and I want a second core running a fixed bare-metal load in parallel to see how it affects the M33. A few things I could not find in the documentation:1. Cortex-M0+ as load generator. Can the M0+ run its own firmware at the same time as the M33 (and Linux on the A35)? Can it exchange data with the M33 (shared memory, mailbox, other), and which memories can it access? Who starts it?2. GPIOs for the M33. I need 2 or 3 pins that the M33 can toggle freely to measure with the oscilloscope. Which pins of the DK can be given to the M33, and what has to be changed (RIF, device tree)?3. Firmware already on the M33. Does the DK ship with any firmware running on the M33 (for example USB-PD, as I saw reported for the EV1)? Can I load my own firmware without breaking the board?4. Cy

Hello ST team,I am designing a custom three-phase inverter using the STDRIVE102BP to drive a 24 V, 26 W BLDC motor. I would like to clarify the recommended external connections for VS, VCC, REGIN_3V3, and VDD.I have reviewed the datasheet and the EVLDRIVE102BP schematic, but I am still confused about the power supply configuration. Are separate external 12 V and 3.3 V supplies required? Do I need to supply VS with an external 12 V source and REGIN_3V3 with an external 3.3 V source?Alternatively, if I use an external 3.3 V supply, should REGIN_3V3 and VDD be connected together to bypass the internal 3.3 V LDO? Does this bypass require any SPI configuration, or is it implemented entirely through the external connections? How is the evaluation board powered in its default configuration? In the EVLDRIVE102BP schematic, REGIN_3V3 is connected to VCC through JP4, with pins 1–2 shorted by default.VS appears to receive power from the external supply through the board’s connections. Initially,

Hello, we’re using the LSMDSOX to detect the shocks on external structures designed to monitor geological phenomena.  We would like to record the acceleration measurements taken immediately before and immediately after the shock into the FIFO buffer.Ideally, we want the detected shock to be positioned in the “middle” of the 512-element FIFO. Unfortunately, we haven't yet determined the best way to configure the system to achieve this behaviour. We tried setting the sensor to Continuous Mode before entering low-power mode and switching to FIFO Mode upon shock detection - this work fine if the shock event occurs few seconds after low power mode is activated; however, it seems that this causes the FIFO to fill up completely if the wait time in low-power mode exceeds a few seconds.We would also like to use the Watermark feature, but it is unclear whether the FIFO will consistently resume recording from the moment the shock was detected.Could someone give any advice? Thank you in advance,Lu

Hey there,I have made a working implementation of the VL53L9 tof lidar sensor for linux.You can find it here:https://github.com/jonferran/vl53l9cx-pi-lidar Jon

Hello,while investigating a HardFault on an STM32U385RGT6Q, I noticed several differences in the code generated by newer CubeMX versions.At the moment I am unsure whether I have overlooked a configuration dependency or whether this is an actual CubeMX code generation issue.Environment:MCU: STM32U385RGT6QFlash Configuration:    Total Flash : 1 MB    Bank 1      : 512 kB    Bank 2      : 512 kBApplication Memory Layout:    0x08000000 - 0x080FDFFF  Application Flash (1016 kB)    0x080FE000 - 0x080FFFFF  Parameter Storage (8 kB)Protection Settings:    Application Area:    Read Only by Privileged Code Only    Parameter Storage:    Read / Write by any Privileged level In CubeMX Version 6.15.0 Flash and MPU initialisation look like this: static void MX_FLASH_Init(void){ /* USER CODE BEGIN FLASH_Init 0 */ /* USER CODE END FLASH_Init 0 */ FLASH_OBProgramInitTypeDef pOBInit = {0}; FLASH_BBAttributesTypeDef FLASH_BBSecInitStruct = {0}; /* USER CODE BEGIN FLASH_Init 1 */ /* USER CODE END FLA

For example, if I edit the ‘Synchronous Predivider’ value for the STM32F030 RTC: Then, say, click on TIM1: Then go click back to the RTC view: My edit is gone! I’ve also been caught-out with this on UART baudrate.I suspect it applies to any numeric-entry field. This should, at least, ask if I want to lose edits. On Win11-Pro.

Hi Experts,I am facing an issue with my custom board based on the STM32H725RGV6. The VCAP voltage remains around 80 mV, preventing the MCU from starting.My intention is not to use the internal SMPS, and I would like to operate the controller in the 100-200 MHz range using the external LDO regulator (As internal LDO not available)Could you please help clarify the following:Can the VFQFPN68 package operate using the internal LDO only, without the SMPS circuitry? Is a VCAP voltage of approximately 80 mV indicative of an incorrect power configuration, damaged device, or missing connection? If the internal LDO is unavailable in this package, would supplying a stable external 1.2 V rail to the VCAP pins while keeping the SMPS disabled/bypassed be a valid solution? Or is the use of the SMPS pins and associated external components mandatory for this device/package?Unfortunately, my PCB layout does not have sufficient space remaining to accommodate the SMPS inductor and related components, so I

hi good day,may we seek your expertise regarding discrepancy on assembly origin in packaging vs country origin on top marking of the chip.is it correct to interpret that China is the country of diffusion(wafer) and Italy is the final assembly and testing?thank you very much for enlightenment.

Hello, I just started in stm32 system, I want to ask for stm32N6 series can use other camera module? such as camera product from Arducam where the product is made for raspberrypi systemwhich uses CSI-2 interface, here product link : https://www.arducam.com/product/64mp-quad-camera-kit/Thankyou

Hi, I’m beginner in this and where’s no a lot of manuals how to do that ,but looks like I’m done everything but still experience some ”hangs” like after run every debug or run I can’t to anything it’s halt and that’s all Would be if somebody will help me with that because it’s makes me crazy , THANKS A LOT to this strange which is spent his/her time to help me) here’s my mcuhttps://www.aliexpress.com/item/1005010547748358.htmlhere’s the log what I get when I try to debug nor run , and I tried different ways to launch it but still I experience “halts” of mcu and strange issues with stm32 programmer (looks like it doesn’t see the mcu screenshot below )    STMicroelectronics ST-LINK GDB server. Version 7.13.0Copyright (c) 2026, STMicroelectronics. All rights reserved. Starting server with the following options:Persistent Mode : DisabledLogging Level : 1Listen Port Number : 61234Status Refresh Delay : 15sVerbose Mode : DisabledSWD Debug : EnabledInitWhile : Enabled Waiting for debugger con

CubeMX Version 6.18.1 (tested with STM32G491VET6) shows no "Clear Input" parameter group for TIM16/TIM17, so the OCREF-clear feature cannot be configured from the tool.The hardware does support it, per RM0440 Rev 9:§31.4.17 "Clearing the tim_ocxref signal on an external event" (TIM15/16/17 chapter) TIMx_CCMR1 bit 7 OC1CE, x = 16..17 (p. 1490) TIMx_AF2 OCRSEL[2:0], x = 16..17 (p. 1505) selecting tim_ocref_clr0..7 Table 76 "Interconnect 3": TIM16/17 ocref_clr sources include the COMP1..COMP7 outputsUse case: cycle-by-cycle peak-current limiting of a synchronous buck (COMPx clears OC1REF; CH1N provides sync-FET freewheel). For comparison, TIM1/TIM2 panes do offer "Use ETR as Clearing Source" / "Clear Input Source".Currently the only workaround is manual register writes in USER CODE (TIMx->AF2 OCRSEL + TIMx->CCMR1 OC1CE), which the .ioc cannot capture.Request: add the Clear Input group (OC1CE + OCRSEL source selection) to the TIM16/TIM17 panes for STM32G4. Image 1: Outline of RM0440

Hi all, I’m searching a method to configure the NVRAM STPMIC25 VINOK_rise param in the 0x90 adress Register (NVM_MAIN_CTRL_ SHR1) As this is a sensitive reg I’m supposing this field and may others are Locked in the NRAM in the DK board from ST. Please I’m considering running Board with 3.3V power Buck Converters. Cheers, Habib 

Hi,I am using the following codes to do system clock initialization on my STM32F411E-Discovery board:  /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; //Use X2 Crystal RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 4; RCC_OscInitStruct.PLL.PLLN = 192; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; RCC_OscInitStruct.PLL.PLLQ = 8; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) But  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)returns time out error.I am sure crystal X2 is connected, but I don’t understand why it gives me time our error. Previosuly I also tried:RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;that also threw time out error, I gave up this configuration because I am not sure if SB14 and SB16 are bridged

Subject: X-CUBE-CLASSB-L4 (STL) — Fault Injection Method for Flash/CPU/RAM Self-Tests on STM32L451CETI am applying X-CUBE-CLASSB-L4 (Self-Test Library, STL) on an STM32L451CET MCU to implement CPU/Flash/RAM self-tests for IEC 60730-1 Class B certification.Main issue: No matter what method I try, the Flash test never passes (always reports a failure / never completes successfully under normal conditions).Certification requirement: Our certification body requires us to demonstrate both the normal (pass) case and the fault (failure) case for each test, specifically by actually altering real values during test execution:CPU test: by actually changing register values during the test Flash test: by changing the CRC value, or modifying Flash memory contents while the test is running RAM test: by modifying RAM contents while the test is runningI understand that ST's recommended method is to use STL_ArtifFailingConfig to perform fault injection. However, this only simulates a failing configurat

Hi,I'm working with an STM32N6570-DK and need the microSD slot (CN13, SDMMC2) to run at 1.8V signaling instead of the 3.3V default. The device I'm connecting only supports 1.8V, and the target speed is modest, around 25 MHz.What's the correct procedure to make this switch on this board?So far I've driven SD_SEL (PO5) high to flip U32, but CN13 pin 3 still measures 3.3V. AN5967 (Getting started with hardware development for STM32N6) section 12.4 points to PWR_SVMCR2.VDDIO5VRSEL together with OTP124 bit 13 (HSLV_VDDIO5), which currently reads 0 on my board.Two things I'm unsure about: Is burning HSLV_VDDIO5 actually required for 1.8V operation, or only to reach the datasheet frequencies?  Does burning it permanently prevent the slot from working with ordinary 3.3V SD cards?  

We are currently working on flashing an STM32L071KZ MCU using the STM32 bootloader.The flashing process completes successfully when using a 64-byte payload. However, when we reduce the payload size to 8, 16, or 32 bytes, we observe unexpected behavior. In each case, only the first 8, 16, or 32 bytes of every 64-byte flash block are programmed successfully, while the remaining writes within the same 64-byte block do not take effect. This pattern repeats consistently for every subsequent 64-byte-aligned address.We have verified that:The correct data is being transmitted to the MCU. The target flash address is incremented correctly for each write operation. The bootloader acknowledges the write commands.Despite this, the flash programming behaves correctly only when using a 64-byte payload.Is there any known limitation or programming requirement for the STM32L071KZ bootloader or flash controller regarding payload sizes? Are there any additional steps or constraints that must be followed w

I have written compact assembler code, with assistance from ChatGPT and Gemini, for the STM32H5E5ZJ to raise its core voltage to VOS0, configure PLL1 and PLL2 and switch system clock to 248MHz.Any comments much appreciated as to the sequencing and safety of this code or any problems seen please.It is tested and working reliably and occupies less than 512 Bytes. At the moment it runs in RAM and only after reset (not to be called later. To run in Flash it must also raise Flash wait states.  The code also configures MCO1 and MCO2, configures SPI1 as master, running at 4MBaud, it puts SPI1 into a delayed loop sending test data readings from TIM2.SPI1 is configured to use PA4 SPI1_NSS, PA6 SPI1_MISO, PA7 SPI1_MOSI and PG11 SPI1_SCK.Any comments much appreciated as to the sequencing and safety of this code.I have used ST Core MX extensively to help build the code by reading MX generated C code. Here is the code, anyone is free to make use of it as a supplement to official ST code if they so

I am using VL53L4CX together with VL53L4CD’s ULD driver. This was discussed before in VL53L4CX using VL53L4CD ULD and it works just fine. I am now willing to improve power-consumption under long-lasting proximity monitoring.I understand that “VL53L4CX is a superset of VL53L4CD” but is it still true for low-power behavior ? Or does the VL53L4CD’s low-power capacity benefits from some permanent factory modification w/r to VL53L4CX ? According to this flyer, only VL53L4CD is rated for ultralow power.   And in case I cannot achieve VL53L4CD’s advertised lowpower specs (down to 50-ish µA) with the VL53L4CX, is it still relevant to use the VL53L4CD’s ULP driver to be as efficient as possible ? and are there some additional tweaks that could be made to this driver in that particular case ?

I’m just getting started with Cube MX and IDE. (MX: 6.18.1, IDE:2.2.0, Debian Trixie platform)I have the Nucleo-144 board with STM32F412GTx device. I’ve tried to configure the TIM1 as PWM,and enabled the interrupts in MX. Generated the code, opened in IDE, built and uploaded to the neucleo board with no significant problems. However, whilst the timer is configured pretty much as specified in MX, the timer is not enabled, none of the interrupts are enabled and the output is not enabled.I can see that whilst a motor control program would not want either the timer or the timer output enabled at boot, not having the interrupts enabled seems strange. I managed to enable these by looking up in the reference manual and manually setting the registers in the debug mode, but that does not affect the Flashed code. (Modifying CR1, DIER and CCER registers)I did find one article describing how to enable the timer, and added that code to the timer init function, but so far I’ve not found the commands

Hi, I’m running the ST BLE Sensor app on an iPhone and when I attempt to change the profile from beginner to expert, it does not take. The result is that many options are grayed out. Am I doing something wrong? Is there a work-around? I don’t have access to an Android device.iPhone 16-Pro iOS 26.62, APP v5.2.6, fp-sns-datalog2 v3.3.0, STEVAL-STWINBX1Thanks, Tony

I attended "Build Your Own Embedded System Workshop From Prototype to Design: Rapid Development with the STM32Cube Ecosystem" at the Embedded World North America in Anaheim, CA last month (Sep 2026). I am looking for slides that were shared during the workshop.

I am enquiring about comparators in STM32G474.For COMP4, it says that the INP can be connected to PB0 and INM can be connected to DAC1_CH1. But when PB0=1.65V and PA4(which is the output of DAC1_CH1)=3.15V , the VALUE bit in COMP_CSR is 1, which should be 0. I measured in from nucleo board and they are exactly the values I expected. And VALUE bit remains 1 when I changed the DAC1_CH1 to other values.It makes me wonder if there is an issue in the manual. It seems that DAC1 is not really connected to COMP4.Thank you!