CubeMX does not expose OCREF_CLR (Clear Input) for TIM16/TIM17 on STM32G4, although the silicon supports it
CubeMX Version 6.18.1 (tested with STM32G491VET6) shows no "Clear Input" parameter group for TIM16/TIM17, so the OCREF-clear feature cannot be configured from the tool.
The hardware does support it, per RM0440 Rev 9:
- §31.4.17 "Clearing the tim_ocxref signal on an external event" (TIM15/16/17 chapter)
- TIMx_CCMR1 bit 7 OC1CE, x = 16..17 (p. 1490)
- TIMx_AF2 OCRSEL[2:0], x = 16..17 (p. 1505) selecting tim_ocref_clr0..7
- Table 76 "Interconnect 3": TIM16/17 ocref_clr sources include the COMP1..COMP7 outputs
Use case: cycle-by-cycle peak-current limiting of a synchronous buck (COMPx clears OC1REF; CH1N provides sync-FET freewheel). For comparison, TIM1/TIM2 panes do offer "Use ETR as Clearing Source" / "Clear Input Source".
Currently the only workaround is manual register writes in USER CODE (TIMx->AF2 OCRSEL + TIMx->CCMR1 OC1CE), which the .ioc cannot capture.
Request: add the Clear Input group (OC1CE + OCRSEL source selection) to the TIM16/TIM17 panes for STM32G4.
Image 1: Outline of RM0440 Showing the section of Clearing the TIM_OXCXREF Signal under TIM16/17
Image 2: Cube MX Config Pane for TIM1 shows the “Clear Input” Row, that allows a selection to choose the source that clears the tim_ocxref signal
Image 3: Cube MX Config Pane for TIM17 doesn’t show the “Clear Input” Row.
