Solved

Good day Sir & Madam, Could you please confirm if MPN STW11NK100Z is free of Dechlorane Plus?We currently have stock with date code 2410 (Year 2024, Week 10). Can you please verify if this specific batch contains Dechlorane Plus?

When I clicked the "Access to MCU Selector" button, the interface did not respond. The pointer just kept rotating to indicate loading. However, when I clicked the "Access to Board Selector" button at this time, the selection interface could be opened.On the board selection interface, when I clicked the MCU/MPU Selector interface, it still showed the situation where the pointer was rotating and indicating a loading process, and I did not enter the MCU selection interface. 

HI,I am working on a board using STM32H573V and have a working solution with UCPD detecting an inserted memory stick and running the MSC class. In an other part of the software I am using PC9 as an GPIO push-pull, low speed output and as soon as I set it to high, the voltage at PB14 (UCPD CC2) drops from 3.3V to 1.5V and my UCPD handler signals a device attached and turns VBUS on even though nothing is attached. There is no other electrical connection between PC9 and PB14 on the board. I am using a TCPP03-M20 for VBUS switching. The board is acting as VBUS source.

Hello ST team,I am working on a NUCLEO-H533RE board with TrustZone enabled and the following boot chain:STiRoT → OEMuRoT → Secure/Non-secure applicationMy device reports SFSP version 1.2.0 (0x01020000).For a secure-boot timing experiment, I would like to use an LSE-clocked RTC as a time reference across a software/system reset.I found the ES0621 erratum titled “Backup domain erased upon reset when STiRoT boot is active and the clock other than LSI selected.”My understanding is that, on affected SFSP versions, STiRoT selects LSI for RTC/TAMP. If the application subsequently switches the RTC clock to LSE, the backup domain is erased during a subsequent reset. Is there any supported initialization or reset sequence that preserves an LSE-based RTC time reference across reset on SFSP 1.2.0, while retaining the STiRoT boot path?I can use DWT for measurements within OEMuRoT, but I need a continuous reference across reset to include the earlier STiRoT stage. Reference: STM32H523xx/STM32H533xx

HelloI am using a Mac. There is software support for stm32cude ide on Mac. But I would like to ask if there is support for Touchgfx application on a Mac.On the website https://www.st.com/en/embedded-software/x-cube-touchgfx.htmlI can not find a link to download the software for Mac.Is there software support for Mac or any other way to run this application? Thank you 

I am unable to change the project name in STM32CubeIde, if i change it and try to open it i get error windows cannot find the file. They are all linked files, may be that is causing the issue, what changes i have to do avoid this error. The project is generated using MCSDK and after generation i am trying to change the project name in CubeIde. 

I have a bunch of following warnings:c:/programs/ARMtools/EmbeddedBSPs/arm-eabi/com.sysprogs.arm.stm32/STM32F1xxxx/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h: In function 'void LL_GPIO_SetPinMode(GPIO_TypeDef*, uint32_t, uint32_t)': c:/programs/ARMtools/EmbeddedBSPs/arm-eabi/com.sysprogs.arm.stm32/STM32F1xxxx/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h:343:22: warning: ISO C++17 does not allow 'register' storage class specifier [-Wregister] 343 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |in several LL headers.Can this please be fixed in some suitable way? One way to do that might be to replace the 'register' specifier by a macro, which would be defined based on the __cplusplus  standard preprocessor macro and its value. A simple version would be to add#if __cplusplus >= 201703L #define register #endifto each header where this occurs, but I am not a C++/build-environment specialist so don't know whether thi

I found an ADC regression on `STM32H563RG` after upgrading from `STM32Cube FW_H5 v1.5.1` to `v1.6.0`.Setup:- MCU: `STM32H563RG`- Old package: `STM32Cube FW_H5 v1.5.1`- New package: `STM32Cube FW_H5 v1.6.0`- CubeMX: `6.17.0`Symptom:- I sample multiple external channels on `ADC2`, including `ADC2_INP0`.- Before the upgrade, `ADC2_INP0` measured correctly.- After the upgrade, `ADC2_INP0` no longer reflects the actual GPIO input voltage, while the other ADC2 channels still behave correctly.This is not a sampling-time or rank-order issue. The problem follows `ADC2_INP0` specifically.The regression appears to come from a change in the LL helper for Channel 0 GPIO switch control.In older FW_H5 code, `LL_ADC_EnableChannel0_GPIO()` always set `ADC1->OR.OP0`, regardless of the ADC instance passed in.In FW_H5 v1.6.0, that helper was changed to set `ADCx->OR.OP0` instead. On STM32H563, that breaks `ADC2_INP0`.What fixes the problem in my testing is:- still enabling Channel 0 GPIO switch cont

  I am noticing a particular issue while measuring the internal temperature sensor using ADC on an STM32H743. Since my Vref tends to vary with temperature, I am internally sampling the Vref to measure the correct reference to the temperature sensing unit.  In the main codeblock that calculates the temperature from the ADC values, I am using the built-in calibrated values for 30C and 110C. Please see below.  My ADC is setup in the following way. static void MX_ADC3_Init(void){  hadc3.Instance = ADC3;  hadc3.Init.Resolution = ADC_RESOLUTION_16B;  hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE;  hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;  hadc3.Init.LowPowerAutoWait = DISABLE;  hadc3.Init.ContinuousConvMode = DISABLE;  hadc3.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;   // 64 MHz / 4 = 16 MHz  // --- CRITICAL POLLING SEQUENCE CORRECTIONS ---  hadc3.Init.NbrOfConversion = 2;  hadc3.Init.DiscontinuousConvMode = ENABLE/*DISABLE*/; // Pauses sequence after each rank  hadc3.Init.ExternalTrigCon

Hello, Our setup uses a VL53L9-based board with an STM32N657 (NUCLEO-N657X0-Q). The sensor streams RAW8 over one data lane at 1 Gbps on VC0. We are using ST’s driver, and 54 × 42 at 100 fps works well.We would like to connect three or four sensors to the N657’s CSI-2 receiver and trigger them through SYNC_IN at staggered times, so their frames do not overlap on the link. Each frame occupies the link for about 0.24 ms of the 10 ms period.We checked the receiver’s lane-state flags between frames. The clock lane remains in high-speed mode throughout streaming, while the data lane returns to the stop state (LP-11). This suggests that the sensors keep driving both lanes, which would prevent them from sharing the same lanes without a MIPI switch or bridge.Could you please clarify the following?Clock-lane mode: Can the VL53L9CX use non-continuous clock mode and return its clock lane to LP-11 between frames? If so, which register or firmware patch enables this? Pin states: Can the MIPI clock a

Hello everyone! I am following the tutorial on st wiki on how to work with STM32MP257F-DK board. Everything was going pretty good, until the “Develop on Arm® Cortex®-M33” part. This is a really important part for me, because the main reason I chose this MPU is because of the additional low-power cortex M33 and M0 co-processors. The part where I am stuck is “Modify, rebuild and reload the firmware for A35-TD flavor”. I have successfully built the “*_sign.bin” file and populated the board with it by using the “Run_Configuration” button. However past 78% the process stops and shows an error that states:“Error in final launch sequence:Failed pre launchFailed pre launchFirmware remoteproc load failed, please:     1. make sure that /lib/firmware on your target has space     2. make sure that /lib/firmware has write access   > you can open a Console View for this..”In the STM32MP2 system a log of these messages are displayed:“[ 2321.306087] remoteproc remoteproc0: powering up m0 [ 2321.307

I have many timers working on out H743VIT6 board, so only have Tim2, 5, 12 and above available.I have many forms of of timer triggered DMA working, but in this case as the system is near to max capacity, I need a DMA event scheduled for 52uS in the future WITHOUT using IRQs which are not time-stable enough for the purpose.So I found that timer 16 in table 98 of the RM0433 manual is show connecting to timer 2, but in CubeMX timer 15 shows no trigger source!So I though I would set up timer 5 to count down 52uS and trigger its DMA stream to write a half word to CR1 of Timer 15, that was setup to pace its own DMA stream.  Now I can get tier 15 triggering and DMA transfering it I enable it via the end of event cllback for timer 5, but DMAing to CR1 of an diabled timer doesn’t seem to work.It’s a very complicated problem! // Arm one amplitude bank, started by a TIM5 countdown delay to trigger DMA write to enable a target timer with DMA streamHAL_StatusTypeDef ArmOneBank(uint32_t *pwm_values,

I am trying to understand the readout protection functionality in the STM32G4 series. When I read the G4 series manual, I get the impression that level 1 protection will protect the flash, option bytes, CCM SRAM and RTC backup registers from JTAG / SWD readout – but curiously not the regular SRAM.Have I understood this correctly?Furthermore, I understand that level 2 will protect the entire chip – but that this is irreversible. So, if I do that to a chip, I can never again use that one for debugging. Not even after a full chip erase, which I’m not even certain that I can perform. As a developer, I see this as pretty much bricking the board.If I am correct that RDP level 1 will not protect the regular SRAM from readout via JTAG or SWD, are there other ways to protect it from JTAG / SRAM probing?

Hi,we are currently using STM32H745BIT6 208 Pin package, now this package is not recommended by ST for new designs, so we are changing to STM32H745II LQFP 176 pin package.is there a way to import the current project IOC file MCU to new MCU. how to do this. if I do again by creating new project it is a huge work. since we are in a production stage this change in new MCU will cause us several software related problem and it will consume again more time.please suggest how to import current project to new MCU Regards,srinath

Hi,I would like to share a solution that may help others using USBX Custom HID on the STM32H723.EnvironmentSTM32H723 STM32CubeMX 6.17 STM32CubeH7 V1.13.0 USBX + ThreadX USB_OTG_HS (Internal FS PHY) Custom HID 64-byte reports IN and OUTProblemThe device enumerated correctly and received HID SET_REPORT requests.A worker thread processed the received command and sent a response using: ux_device_class_hid_event_set(&hid_event); After the first IN report, the application appeared to hang.The CPU spent nearly all its time inside: OTG_HS_IRQHandler() and ThreadX tasks no longer received meaningful runtime.Debugging ResultsThe following registers were observed:DAINT     = 0x00000002DIEPTSIZ1 = 0x00080040DTXFSTS1  = 0x00000000 This indicated that EP1-IN had a pending 64-byte transfer and the Tx FIFO remained blocked.HAL_PCD_EP_Transmit() returned:HAL_OKbut the transfer never completed. Root CauseCubeMX generated no FIFO configuration for the USB OTG HS peripheral.The following functions wer

We are considering using a WB05KN as a BLE coprocessor in an STM32H573 design.  I found the section in your wiki describing paths for Bluetooth certification.  It says that no testing is required if a precertified module is used, or the recommendations and layout in AN5526 have been followed to the letter.Separately, all intentional radiators (in the US) must pass FCC testing, but if one uses a precertified wireless module and specified antenna, then the incorporating product can simply cite the certification of the wireless module.I want to clarify… are these two sets of testing (Bluetooth qualification as discussed in the ST Wiki, and FCC intentional radiator testing) two different sets of testing entirely?  That is, if we do a chip-down WB05KN design according to AN5526, would we still have to do FCC intentional radiator testing, even though we would not need to perform Bluetooth certification testing?If I’m understanding that correctly, is it then true that the only way to avoid FC

I'm in debug mode in STM32CubeIDE.On the SFRs tab in the upper right corner, I want to enable UART4 and check the register status.But I only see UART-related items: LPUART/USART1/USART2/USART3.Why can't I find UART4?My MCU is an STM32C551RCT6.I'm very certain this IC has UART4

I’m making AOI program for STSAFA110DFSPL02 and would like the correct top marking because I couldn’t find it in the datasheet.The received part has SF3C B317 marked in the top side and need to confirm that is correct or not.

Hi STMicro team,On usage of MPN:M24LR64E-RDW6T/2, recent datecode: 102026 (WWYYYY)  , we find below difference:The difference is  C to D change in the chip RFID module :Old Build BoardRFID Memory Code: E0025C9196D23D96 Date Code: 2336 Result: 100% Pass RateNew Build BoardRFID Memory Code: E0025D71B0C4273 Date Code: 2610 Result: Boards Failed During FCT (100%) The customer has requested clarification regarding the change from "C" to "D" in the RFID memory code,.Could you please check with the supplier / STMicroelectronics and confirm the following:Is this only a product code/marking change? Is there any change in component characteristics, specifications, firmware, or functionality compared to the previous build?

Hi there I have a STM32MP257f-DK board running the latest Linux, and I’m trying to output to a waveshare 9.3” HDMI display at its native resolution. 1600x600I can output to it at 1920x1080. and I can output to the display from my Mac at it’s native 1600x600. I see a slight flicker when I try send video then black. then the display goes to sleep. So the display is losing sync.linux reports the output is working, but it seems it’s something to do with the ADZ7xx chip.any ideas?

I am currently developing a USB Mass Storage application using the STM32H563ZI with the following architecture:PC ← USB ← NUCLEO-H563ZI ← SD CardThe SD Card and USB Device have both been tested separately, and each works correctly on its own.However, after integrating the two, I would like to use USB MSC to expose the SD Card connected to the STM32H563ZI as a removable storage device on the PC. The PC is currently unable to recognize the SD Card properly.I would like to ask if there is any example code or reference project for the STM32H563ZI that demonstrates USB MSC with an SD Card.Thank.

Hi,On the SR6P3C4 page (https://www.st.com/en/automotive-microcontrollers/sr6p3c4.html) there's a databrief. But not much about a datasheet, specification, or any deeper information about the modules associated with it. Is there a way to access those?Also (still related to the first question), the data brief does say something about maximum junction temperature of 165C, with a note:Nominal specification up to 150 °C. Delta specification up to 165 °C.I'm not sure to understand what does the delta specification means.Thank You

I’m using CubeProgrammer v2.23.0 with the SDMMC_STM32N6570-DK external loader (no additional loaders). I have the boot switches in the boot0=L, boot1=H positions. I have looked at all the posts similar to this one, however none of the suggested fixes have helped.When I try to program the eval board I get the following error message ... NOTE: I am able to download a new GUI directly from TouchGFX to external flash and it is fine. So, this is obviously an issue with CubeProgrammer/settings within? 

Hello am designing a 6S battery pack (25 V nominal) around the BQ40Z80 and would appreciate your feedback on my schematic before I proceed to layout. I used the BQ40Z80 EVM reference design (datasheet Figure 7-1) as a starting point and adapted it for a higher current.Design summary -Cells: 6S (VC1–VC6), with 100 Ω / 100 nF RC filters on each cell input.- Current: 60 A continuous, 80 A peak (the charge current is lower).- Current sense: 1 mΩ shunt on SRP/SRN, which gives about 75 mV at 75 A. This is within the ±100 mV input range of the device.- Protection FETs: 3× BSC014N06NS in parallel on the CHG side and 3× in parallel on the DSG side, in a common-drain back-to-back configuration.- Gate drive: single gate resistors per FET (1 kΩ on the CHG side, 12 kΩ on the DSG side), 10 MΩ gate-source resistors, and clamps on the gate-source of the DSG FETs.- Pre-charge/pre-discharge: P-channel MOSFET (Q41) in series with a 100 Ω / 3 W resistor (R140), driven by a BSS138 from LEDCNTLA (PCHG is no

Hi ST Community, I discovered nucleo board 2 weeks ago because I want build spectrometer using a Toshiba TCD1304DG CCD sensor.I’m reaching out because I need your help understanding how to drive this ccd sensor. I’ve read datasheet and projects on internet to get a general understanding of how to operate this sensor. However, there are a few points I’m still unsure about. Could you please help me clarify the following questions? Here is the datasheet : https://toshiba.semicon-storage.com/info/TCD1304DG_Web_Datasheet_en_20260520.pdf?did=13709&prodName=TCD1304DG 1. Is my understanding of the acquisition sequence correct?My understanding is that, to read all 3,694 pixels using a hardware timer, the ADC, and DMA, the acquisition sequence should be as follows: Set ICG LOW. After 500 ns, set SH HIGH. After 5,000 ns, set SH LOW. After another 5,000 ns, set ICG HIGH. Read all 3,694 pixels from the OS pin. The master clock (M) runs continuously, shifting the pixel values out sequentially, w