STM32H533 SFSP 1.2.0: can a Non-secure RTC avoid the STiRoT backup-domain reset issue with LSE?

[parato]

Hello ST team,

I am working on a NUCLEO-H533RE board with TrustZone enabled and the following boot chain:

STiRoT → OEMuRoT → Secure/Non-secure application

My device reports SFSP version 1.2.0 (0x01020000).

For a secure-boot timing experiment, I would like to use an LSE-clocked RTC as a time reference across a software/system reset.

I found the ES0621 erratum titled “Backup domain erased upon reset when STiRoT boot is active and the clock other than LSI selected.”

My understanding is that, on affected SFSP versions, STiRoT selects LSI for RTC/TAMP. If the application subsequently switches the RTC clock to LSE, the backup domain is erased during a subsequent reset.

 

Is there any supported initialization or reset sequence that preserves an LSE-based RTC time reference across reset on SFSP 1.2.0, while retaining the STiRoT boot path?

I can use DWT for measurements within OEMuRoT, but I need a continuous reference across reset to include the earlier STiRoT stage.

 

Reference: STM32H523xx/STM32H533xx device errata — ES0621

Thank you for your clarification.

[Jocelyn RICARD]

Hello ​@parato ,

This issue was fixed in SFSP 1.3.0 because there was no possible useful workaround.

The workaround proposed in errata sheet

“After the reset, restore the backup domain data and the RTC clock source.”

Cannot address your timing measurement.

Only solution I can see is to get chips with SFSP 1.3.0

Best regards

Jocelyn