How NMI in STM32 works? How to trigger this interrupt?

[sholojda]

Can you explain me how to trigger NMI in STM32F103 MCU? I am wondering what is the purpose of this interrupt? And Why it is called interrupt because interrupts are trigger by peripheral.

Can you show me an example how to trigger it?

Thanks so much

[Uwe Bonnes]

NMI is only linked to internal sources, like clock failures or double flash errors, depending on device. Probably you can assert it with the appropriate Cortex registers. But mostly from programms there is no need to use NMI as there are other possibilities.

[sholojda]

Thanks for answering.

I am beginner and i am trying to understand all this faults and interrupts in STM32.

When can NMI happen? I'm asking because i have read that it can be use ( i mean NMI) with Watchdog for example.

[berendi]

According to the reference manual, NMI on the STM32F103 is issued by the clock security (CSS) subsystem only. There is no mention of NMI in the IWDG and WWDG chapters. Where did you read it?

[berendi]

> Why it is called interrupt because interrupts are trigger by peripheral.

Because it is triggered by a peripheral. Even on-chip components like clock control are considered peripheral.

> Can you show me an example how to trigger it?

According to PM0056 Cortex®-M3 programming manual,

SCB->ICSR |= SCB_ICSR_NMIPENDSET;

should trigger it. Or configuring HSE and CSS in RCC, and shorting one of the HSE pins to something else, but it might void your warranty.

[sholojda]

to be honest I have read this not in RM of STM32 but in Definite Guide. I think (now) it concerned generally Cortex M. Thanks anyway

Can you point me where in RM i can read obout CSS. I can not find it.