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I am trying to disable the write protection on an STM32G431K (on a Nucleo-G431KB) by settings the option bytes using CubeProgrammer:However, “Apply” fails with the log showing:11:14:40:365 : Option byte command : -ob WRP1A_STRT=0x3f WRP1A_END=0x0 11:14:40:367 : qCmd : -ob WRP1A_STRT=0x3f WRP1A_END=0x0 11:14:40:367 : PROGRAMMING OPTION BYTES AREA ...11:14:40:368 : Database: Config 0 is active.11:14:40:368 : Bank : 0x0011:14:40:368 : Address : 0x40022020 11:14:40:368 : Size : 84 Bytes11:14:40:373 : halt ap 0 11:14:40:381 : Loader write option bytes...11:14:40:381 : Init flashloader...11:14:40:381 : halt ap 0 11:14:40:389 : run ap 0 11:14:40:390 : halt ap 0 11:14:40:396 : run ap 0 11:14:40:420 : Reconnecting...11:14:41:549 : ST-LINK SN : 00190036313351123630373911:14:41:549 : ST-LINK FW : V3J17M1011:14:41:549 : Board : NUCLEO-G431KB11:14:41:550 : Voltage : 3.27V11:14:41:739 : Error: Unable to get core ID11:14:41:739 : Error: Cannot connect to acce

hiI installed version 5.1.1 today and reactivated the license key, but I got the following error. nanoedge ai studio license has reached its activation limit Is there a solution?   I installed version 5.1.1 today and reactivated the license key, but I got the following error. Is there a solution?

Pls help with FIT rate value for below components:STM32N657X0H3Q    - MCU LSM6DSVTR          - IMU Sensor M24M01E-FMN6TP    - EEPROM ST4SI2M0004TPIFW    - eSIM

 I am seeing behavior on an STM32G474 that I cannot explain and would appreciate if anyone has seen this before.SetupMCU: STM32G474 (Nucleo-G474RE) COMP6   Positive input: PB11 (COMP6_INP / ADC1_IN14) Negative input: DAC2_CH1 HRTIM Fault 3 source: Internal Fault (FLT_Int) from COMP6 Fault filter: Disabled Fault counter threshold: 0 Fault polarity: Active HighDAC ConfigurationDAC2_CH1 configured as:Normal mode Connected to on-chip peripherals only Output buffer disabledRuntime code updates DAC2 every 1 ms:HAL_DAC_SetValue(&hdac2,                 DAC_CHANNEL_1,                 DAC_ALIGN_12B_R,                 dac_value);Verification PerformedVerified COMP6 configuration registers. Verified DAC2 DOR register contains expected value. Verified HRTIM Fault3 is the only enabled fault source. Disabled ADC sampling on PB11 (no change). Verified fault polarity behavior. Verified comparator output on a GPIO pin.ObservationWhen monitoring the COMP6 output pin directly, the comparator switche

Hi all,I came across an older thread here ("Anomaly Detection on ISPU", ISM330ISN) where the conclusion was that NanoEdge AI's learned knowledge cannot be preloaded onto the ISPU — the "Include knowledge from benchmark" option isn't available when targeting the ISPU, because the model has to relearn after every power cycle. One of you confirmed this is expected behavior given the ISPU sits directly on the sensor with no on-board non-volatile memory for it.I'm doing research on vibration-based bearing fault detection (a manuscript is currently under review at Mechanical Systems and Signal Processing, with validation across four public datasets — CWRU, Huang–Baddour, XJTU-SY, Paderborn), and this relearning constraint is directly relevant to what I'm working on: detectors whose healthy-state reference is small enough to be committed to flash and restored instantly, with no relearning window after a restart.Two questions for the community / ST team:1. Does this same constraint apply to th

I am trying to use the STWIN.box - SensorTile Wireless Industrial Node Development Kit to detect vibration on X-ray tubes. I know the sensor has screw holes but the tube doesn’t have screw holes. I was wondering what other options I had for mounting?

It’s mentioned in RM0456 rev7 that manual trim must be done for device variants except STM32U535/545; U575/U585 Rev.X: However in CubeMX 1.8.0 manual trim is only applied for these devices, which only applies to half of the family: /* This is only needed for some devices/rev. */ if (((dev_id == 0x482UL) && (rev_id == 0x3000UL)) || ((dev_id == 0x481UL) && (rev_id == 0x2001UL)) || ((dev_id == 0x481UL) && (rev_id == 0x3000UL)) || ((dev_id == 0x476UL) && (rev_id == 0x1000UL)))For example my Nucleo-U5A5ZJ-Q board has dev_id=0x0481 and rev_id=0x3001 so the manual trim is not applied.Which one is correct ?

For the SMPS mode of the STM32H563MIY3Q, the datasheet recommends an inductor with an RMS current (Irms) rating of 1.4 A. However, the actual core current is only 50 mA. Is it acceptable to select an inductor with a lower Irms rating, such as 500 mA?

I am using an STLINK‑V3ISOL and need compatibility with a setup/documentation that specifies ST‑LINK/V2.Is there any jumper setting, hardware configuration, or firmware option that allows the STLINK‑V3ISOL to operate as an ST‑LINK/V2 device?If not, is there a recommended adapter or pin mapping to make the V3ISOL interface compatible with a V2 connector/pinout for SWD/JTAG debugging?Any guidance or experience would be appreciated.

Dear ST Community,I’m currently working with an ALIENTEK STM32MP257 development board and ran into an issue when deploying a model converted via the ST Edge AI online tool.The original model is a plant disease recognition model from the ST model zoo (in .tflite format). I used the ST Edge AI webpage to convert it to an .nb model for deployment on my STM32MP257 board. However, when I test the converted .nb model, the inference output is unexpected: it only predicts two classes — “Background_without_leaves” and “Corn__Northern_Leaf_Blight” — both with relatively high confidence. This happens regardless of the input image.In contrast, when I run inference directly using the original .tflite file on the same test images, the results are correct and show proper class diversity.I double-checked my test code and also consulted AI assistance, which suggested that the converted .nb model might be problematic.I’ve attached a compressed file conta

Hi,what would be recommended way to override internal LDO which is used for VDD11/VCAP preparation? Because of thermal management, we prepared external LDO to lower internal MCU temperature. In H5 family, there was an BYPASS bit in PWR management. Maybe shall I change Vos to lower level to let higher level LDO win? Or would you have other way :) Thanks!JM

HIST EDGE AI can generate projects for various development boards based on the STM32U0 (e.g., NUCLEO-U083RC). However, the STM32U0 does not appear in the list of supported MCUs (only U3 and U5 are supported). Am I doing something wrong? BRGilberto

Hello,I am using the ST25R200 evaluation board with the STSW-ST25R020 firmware package.I am planning to develop a custom Python GUI that displays a specific text string whenever an NFC tag is detected by the board. To achieve this, I want to modify the C firmware so it actively streams out a text string via UART/VCP as soon as a tag enters the field.Could you please guide me on the following?Which specific source file and function in the STSW-ST25R020 package handle the successful tag detection/inventory loop where the tag's UID is retrieved? Where is the best place to insert a custom printf or logging function to stream this text data out via UART immediately upon detection? Thank you very much for your help!

Hi,I am trying to install ST Edge AI Core 2.0.0 for an STM32N6 project. During the installation process, the installer asks me to specify the ST Neural-Art package archive.However, I cannot find the ST Neural-Art archive on this page:https://www.st.com/en/development-tools/stm32n6-ai.html#overviewI only found the ST Edge AI Core download, but not the separate Neural-Art archive required by the installer.Could you please let me know where I can download the correct ST Neural-Art archive compatible with ST Edge AI Core 2.0.0?Thank you.

 Hi Team,I am currently working on a Driver Monitoring System (DMS) project using the STM32MP257F-DK board, and I have successfully integrated the OV5647 camera sensor.At this stage, I am facing an issue related to ISP calibration. The camera is currently running with auto exposure enabled, due to which the frame contrast is not constant for any detection. To stabilize and properly tune the image, a fixed YAML calibration file is required. However, a suitable YAML file for the OV5647 sensor is not available.From my understanding, the YAML calibration file needs to be generated using the ISP tuning/calibration tool. However, I tried following the complete process mentioned in the Wiki page  documentation, but the ISP tool is not detecting the board, which is blocking further progress.Could anyone please guide me on the following:How can I generate a custom YAML calibration file for the OV5647 sensor using the ISP tool?Is there any alternative or manual method to create the YAM

I have an axf file generated by vscode keil studio, then I followed follwoing tutorial to debug in vscode stm32cube ide.How to debug an external .elf file in VS Code | CommunityThen it triggers hard fault, and debugger shows `SystemCoreClock` is not correctly initialized, when it enters into `main`, the value is initialized to `(uint32_t) -1`.If I terminate gdb and soft reset it in cube programmer, it works fine, it also works fine when I debug it in vscode keil studio. The project is a simple cubemx STM32F407 generated project, and enables serial wire debug, the code in main infinite loop is just two ITM_SendChar. Update:It only occurs in first time launch, if it enter hard fault then click reset target, it works fine, but data values of SystemCoreClock and uwTickFreq are still -1. 

On a secured STM32H7Sx device (in CLOSED or LOCKED product state), what is the recommended way of passing volatile data to lower HDPL levels?According to the reference manual, the SBS_RSSCMDR register can be used to pass volatile data from HDPL 1, 2 or 3 to HDPL 0 (RSS), so that part of the answer is covered:Bits 15:0 RSSCMD[15:0]: RSS commandThe application can use this bitfield to pass on a command to the RSS, executed at thenext reset.But what if you want to pass volatile data from HDPL 2 or 3 to HDPL 1?(E.g., HDPL 2 wants to call into HDPL 1 so HDPL 2 first needs to write some volatile command somewhere, then execute a reset, then HDPL 0 (RSS) boots, then HDPL 1 boots and picks up the volatile command from somewhere.)SBS_RSSCMDR cannot be used because RSS will interpret this value as well, and RSS might clear this value at the moment it boots HDPL 1.

Hello,I would like to report a documentation issue in RM0511 Rev6, section 15.9 (LCSC register map, Table 38).The introductory text states:> "The green cells indicate the register is in the VDD12o power domain. This implies those registers are not reset on Deepstop exit."However, in Rev6 the color highlighting is missing from the table — it is not possible to identify which LCSC registers are in the VDD12o power domain. This information is critical for correct Deepstop/low-power mode implementation, as registers in the VDD12o domain retain their values across Deepstop while others do not. **References:**- RM0511 Rev6, section 15.9, Table 38- RM0511 Rev5, section 15.9, Table 39Thank you.

Hi,the cubemx HRTIM configuration will not let me set the set sources for Output 2, even though deadtime insertion is turned off.I had previously enabled it, and now disabled it. Since then I am unable to add a set source for Output 2.See the attached screenshots and .ioc file.I am using version 6.17.0

I'm investigating a suspected flash corruption/ECC issue on an STM32H743.A read from flash address 0x081F0000 consistently causes a fault. The problem is that I'm not fully confident that the fault status registers can be trusted after the event, so I'm looking for a diagnostic approach that does not rely entirely on the captured fault information.Known facts:Accessing 0x081F0000 triggers a fault. ECC_FA2R does not show a failing address. STM32H7 flash ECC is evaluated only when flash is read. ECC granularity is 32 bytes (256 bits).My main question is:If I suspect flash corruption or an ECC problem, but do not fully trust the contents of CFSR, HFSR, BFAR, SR2, or ECC_FA2R after the fault, what is the recommended way to diagnose the problem?Would you:Perform a controlled BusFault-protected flash scan in 32-byte steps? Use HAL_FLASHEx_ComputeCRC() over the suspect region? Dump the entire flash bank via SWD/JTAG and verify externally? Use some other method?Has anyone seen a corrupted flas

I am trying to do OTA programming modifications using the DUAL bank feature of my STM32U575 IC with 1Mbyte of memory.I have successfully done this when the program starts in BANK 1 and I reflash BANK 2. I change the User Option byte to OB_SWAP_BANK_ENABLE and the board reboots and successfully runs from BANK 2.Now, on the next firmware update, programming BANK 1 when I am operating from BANK 2 the HAL_FLASH_Program command fails on the first byte.The erase code is attached and it is very similar to others I have found on GIT for other products. Does the U5 have an inherent defect? any help would be greatly appreciated.

Title shortened from:"With the STM32U545RE, unable to erase the correct Flash Bank, using HAL_FLASHEx_Erase(), when attempting to switch from Bank2 to Bank1".Please keep the title short. Testing is done with the Nulceo-U545RE-Q board having 512KB Flash organized in two Banks. Each Bank has 32 pages of 8KB each. Flash Bank1: 0-31 pages. Flash Bank2: 32-63 pages. I could switch-over from Firmware-Version1 executing in Bank1 to Firmware-Version2 executing in Bank2. I verified that Firmware-Version2 was executing correctly even after hardware reset and power cycle.Attempting to switch-over  from Firmware-Version2 executing in Bank2 to Firmware-Version3 executing in Bank1 fails as I end up erasing the Bank with the currently executing software(Firmware-Version2). I checked the setting of the SWAP_BANK bit and then erased the Bank, using the code below:  /* Get the boot configuration status */ HAL_FLASHEx_OBGetConfig(&OBInit); /* Check Swap Flash banks statu

Hi, Could you please confirm whether an external NFC antenna can be connected to the X-NUCLEO-NFC08A1 board? I see P200 and P202 in the schematic, but it is not clear to me whether these are intended for external antenna connection or only for optional/test points. If an external antenna can be used, could you explain how the on-board etched PCB antenna should be disconnected from the ST25R3916B antenna path, where the external antenna should be connected instead, and what antenna inductance or electrical parameters should be targeted before tuning the matching network?Thanks!Best regards, Jose 

Hello team, Another day, new same issue. :pensive_face:I have setup the DCMIPP PIPE 1 for the stm32n6570 DK, so that it dumps frames in address 0x34200000 which maps to SRAM3 begin address I have enabled bothe the memories SRAM3 and SRAM4 but with out software erase, I used the MX tool for project generation , I goal is to mimic the Continous Mode example provided by ST, I have read about the appilication notes getting started with DCMIPP and the afew sections of intrest form the RM for the deve board on the topic. I however face the challenge  as stated in the Post Title, there Is are no interrups being called yet I set up the global intterrups for both the Pixel pipe and the CSI interfacing, "Still as shown in in the generated files" and set the clocks for the DCMIPP is set to 300Mhz and the CSI interface I had to manualy try setting up the  input clock freq for the IMX335 module to 20Mz as the MX tool does not provide for its setting, but I have this code commented out as there was

We are currently working on a project using the STM32H750IBT6 microcontroller interfaced with a single-bank Quad SPI NOR Flash (MT25QL512ABB) on our custom board. The QSPI interface is operational.However, we are facing an issue with the external loader. While the same external loader setup works correctly with the STM32H750 development board using the same two MT25QL512ABB Flash memories, it fails to function on our custom board.Development board QSPI schematic: Our custom board QSPI schematic: For reference, we are used the external loader implementation for development board from the following link: https://controllerstech.com/w25q-flash-series-part-8-quadspi-external-loader/ We request your support in:Verifying if our schematic connections for the QSPI interface may be contributing to the issue.Identifying any possible hardware or configuration-related causes for the external loader failure.