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Tool: ST Edge AI Core v4.0.1-20581 (7ed50de05), target stm32n6Neural-ART compiler: 1.1.3-275Runtime: ST Neural ART (LL_ATON api) v1.1.3, atonn-v1.1.3-275-g6770925dBoard: STM32N6570-DK, device 0x486, Cortex-M55Host: Windows 11, STM32CubeProgrammer 2.23.0, gnu-tools-for-stm32 14.3.1WHAT HAPPENSA 23x60 -> 30x5 INT8 TCN, generated for stm32n6 with the Neural-ART compilerand run on the NPU, returns an output that is not the INT8 graph's.This is not an application bug. "stedgeai validate --mode target", run againstyour own NPU_Validation project with your own random stimulus, reports theboard's output as essentially uncorrelated with the reference model thenetwork was generated from:  acc=n.a. rmse=2.543027878 mae=1.976331592 l2r=1.100639820  mean=-0.346161 std=2.520198 snr=-5.872663 nse=-2.889206 cos=0.091053cos 0.091 is no correlation. snr -5.87 dB is noise above signal. nse -2.889 isworse than answering with the mean of the reference. l2r 1.10 is an errorlarger than the quantity it is

As i was going through the tutorialhttps://dev.st.com/edge-ai-docs/general/latest/en/docs/tutorials/how-to-deploy-ai-model-stm32n6-neural-art.htmli have faced issues in the linker script.The tutorial’s linker-script example places model data in EXTFLASH using the *_atonbuf.xSPI2*(.rodata*) pattern. In my generated project, however, the model weights are emitted in Application/User/AI/network.o as .rodata._ec_blob_network_* sections. Those sections didn’t match the example’s pattern, so the general .rodata* rule placed them in ROM instead.This caused .rodata to extend past the ROM boundary at 0x70180000 and overlap .AI_XSPI2. Adding *(.rodata._ec_blob_network*) to the .AI_XSPI2 section moved the model blobs into EXTFLASH and fixed the link.Please consider updating the tutorial to mention that generated model-section names can differ, and show how to check the linker map and route the generated model blob sections to EXTFLASH.the solution for me was to update the linker script with this.

Main goal is to measure the RMS value of the mains, first question is can i perform the calculations using floating point or fixed point? The RMS requires the sqrtf function, can i use the function due to its number of cycles?

After upgrading from CubeIDE v1.17 to v2.2 I have problems debugging my H563 custom board:When I hit a breakpoint, sometimes I cannot Resume/Step Over/Step In. When running, sometimes I cannot Terminate or Disconnect and must relaunch the IDEDid not have these problems with CubeIDE v1.17. Versions with CubeIDE v2.2:gdb 7.14 ST-Link V3J17M11I would like to run the CubeIDE v1.17 gdb but see no way to edit the GDB server command line options.Anyone else encounter this?

I am evaluating the LDQ40PUR (adjustable version) and there is some ambiguity in the datasheet for setting the output voltage.The datasheet states:The resistor divider should be selected as follows: VOUT = (1+R1/R2)*VADJ, considering IADJ negligible. What is VADJ? Should this be VREF (1.2V)? I assumed VADJ = VREF = 1.2V, and calculated my output with the following values:R1 = 340kOhmR2 = 102kOhmVOUT = (1+340k/102k)*1.2V = 5V However, when I built the circuit with these values, I am not getting this value at the VOUT pin. When VIN is 3.6V or higher, I get VOUT = VIN (e.g. VIN=7V, VOUT=7V) Here is the schematic for my circuit:Schematic for LDQ40PUR test circuit 

I’m developing a motor driver that uses hall quadrature encoder on the motor shaft. I implemented the code described in a tutorial here… https://deepbluembedded.com/stm32-timer-encoder-mode-stm32-rotary-encoder-interfacing/The example runs fine with PF12 (TIM20_CH1) and PF13 (TIM20_CH2) connected to the quadrature signals.Except, if I assign User Labels M3_HALL_A and M3_HALL_B respectively, the initialization code is not properly created and the PF12 and PF13 remain in their reset configuration (pin mode analog MODER values are 0x03).Is there some extra step required if User Labels are assigned, or is this a bug to be fixed?Thank you.

Board: NUCLEO-WL33 Toolchain: CMake + arm-none-eabi-gcc CubeMX version: 6.17.0 STM32CubeIDE version: 2.1.1I am trying to run a basic STM32WL33 project generated by STM32CubeMX using the CMake toolchain instead of the native STM32CubeIDE project format.The same CubeMX configuration, when generated as a native STM32CubeIDE project, works correctly and reaches HAL_Init() in main.c without any issue.However, when using the CMake-based output, the firmware crashes during startup andnever reaches main().SymptomsDebugger halts inside SystemInit() at line 200 (system_stm32wl3x.c), or jumps to an address outside valid memory (0x100004ee — inside the ROM region 0x10000000–0x100017FF) Is there a known-good CMake startup/linker reference for the STM32WL33?

Hi,MC SDK 6.4.1, STM32G431, three shunt configuration.I genrated code with workbench with open loop debug.I am able to run ACIM motor in openloop voltage mode.Now, i need to allow overmodulation to utilise 100% VBUS.In MCWB I set DPWM overmodulation flag, generated code and mergerd changes with my actual application code.I am expecting thate PWM waveform should be for DPWM but on CRO i see standard SVPWM.Can anyone help to enable DPWM and utilise VBUS 100% using overmodulation? Thanks & Regards,Ketan Patel 

Hi, Thank you for your support. I was able to get VL53L4CD_GUI working using the firmware file:VL53L4CD_PSNRun_F401.bin However, the connection is very unstable and I am having difficulty using the GUI reliably. Current status:1. I programmed VL53L4CD_PSNRun_F401.bin into the NUCLEO-F401RE using STM32CubeProgrammer.2. Initially, VL53L4CD_GUI could not connect.3. I noticed that if I enable the option "Run after programming" in STM32CubeProgrammer during programming, VL53L4CD_GUI sometimes connects successfully.4. When the connection succeeds, the GUI displays:   Device Name : VL53L4CD   API Version : api rev 0.2.2 build 3   and I can acquire ranging data correctly.5. However, after power cycling the board or reconnecting later, the GUI usually shows:   "Failed To Connect to Nucleo Board: Com Port Not Detected"6. In Windows Device Manager, the board is still visible as:   "STMicroelectronics STLink Virtual COM Port"   and the COM port is recognized correctly.7. Reprogramming the same fir

I am a newbie with the concept of function pack.I would like to  create an from scratch starting from the fp-sns-stbox1. I would like to start by  installing /importing fp-sns-stbox1 and use it’s source ( such as drivers, bsp etc..) to build ny application.All the documents that I see describes the features of the fp, but no guide on how to install/import so that I can modify the code toimplement my application. Tried to  import then compile, which  gives me error ‘no make file’ etc..What is the best way to accomplish my objective?

When Comparator is configured, the init sequence do not generate the option for Positive input selection one has to add this line manually, depending on the pin selected as INP. hcomp1.Init.InputPlus = COMP_INPUT_PLUS_IO1; or hcomp1.Init.InputPlus = COMP_INPUT_PLUS_IO2; orhcomp1.Init.InputPlus = COMP_INPUT_PLUS_IO3;  and so Comparator do not work if not checked. I am using CubeMX version 6.18.1

On the STM32F407G-DISC1, I try to flash the MCU through USART1 using PA9 (TX) and PA10 (RX) with STM32CubeProgrammer.BOOT0 is connected to 3.3V (HIGH), and BOOT1 is connected to GND (LOW). I have also disconnected the resistors and capacitors connected to PA9/PA10, and there are no external connections to these pins.However, I am unable to connect to the MCU through PA9/PA10 using STM32CubeProgrammer. Is there any additional hardware connection, configuration, or limitation that I need to consider for using PA9/PA10 for UART bootloader flashing on the STM32F407G-DISC1?

I have implemented streaming speech recognition on the STM32N6, with a model designed specifically for the constraints of this microcontroller and its NPU.The STM32N6570-DK listens to its on-board microphone and prints the text on the display. It recognizes any English words, not a fixed list of commands, and works with no network connection. The word error rate on LibriSpeech test-other is 14.84% with no language model.Source code, model weights and ready-to-flash firmware: https://github.com/fotonik-sk/stm32n6-asr

Hello ST team,I am working on a NUCLEO-H533RE board with TrustZone enabled and the following boot chain:STiRoT → OEMuRoT → Secure/Non-secure applicationMy device reports SFSP version 1.2.0 (0x01020000).For a secure-boot timing experiment, I would like to use an LSE-clocked RTC as a time reference across a software/system reset.I found the ES0621 erratum titled “Backup domain erased upon reset when STiRoT boot is active and the clock other than LSI selected.”My understanding is that, on affected SFSP versions, STiRoT selects LSI for RTC/TAMP. If the application subsequently switches the RTC clock to LSE, the backup domain is erased during a subsequent reset. Is there any supported initialization or reset sequence that preserves an LSE-based RTC time reference across reset on SFSP 1.2.0, while retaining the STiRoT boot path?I can use DWT for measurements within OEMuRoT, but I need a continuous reference across reset to include the earlier STiRoT stage. Reference: STM32H523xx/STM32H533xx

Hello everyone,I’m working with the STM32U5G9J-DK2 and trying to implement a Bootloader + XIP (Execute-In-Place) application architecture using the external flash.Target setup:A minimal bootloader running from internal flashThe main application linked to and executing from external flash (memory-mapped at 0x90000000)The main motivation is to free internal flash and validate this approach for a future MCU with very limited internal flash.What I’m specifically looking for help withProper CubeMX / .ioc configuration for the bootloaderWhich peripherals must be enabled (RCC, PWR, ICACHE, OSPI, etc.)Which peripherals should not be enabled to avoid conflicts with the XIP appAny STM32U5-specific gotchas when initializing OSPI for XIPProper configuration of the application projectRecommended changes to the application .iocWhat initialization should be removed from the app (HAL_Init, clock, OSPI, FLASH, etc.)Reference samplesSTM32Cube examples that demonstrate a full bootloader + XIP app flow on

I could not find any literature about this so I decided to post on community. When I activate ISM303DAC I experience noise on other parts of the board. At first, I thought this is caused by the communication, but it is not. Also, there is no noise when only the accelerometer is enabled. My theory, the noise is caused by the set/reset function...I haven’t been able to prove my theory, yet. I am working on it. So, I am asking if anybody experienced the same problem. Thanks for the feedback. Your thoughts and comments are welcome.  

Hello,I am using an STM32G484RE with HRTIM running at 160 MHz, configured as follows:Timer B runs continuously with prescaler HRTIM_PRESCALERRATIO_MUL32. External event EEV7 comes from GPIO PB4. EEV7 uses rising-edge detection, with digital filtering disabled. EEV7 resets Timer B’s counter. The same EEV7 event sets Timer C’s output TC1. TC1 SET triggers Timer B capture 1.I need to understand the timing between the external GPIO edge, Timer B counter reset, and TC1 SET/capture.I found the following differences in RM0440:The older timing diagram, Figure 217 in the edition corresponding to English Rev 7, shows 2–3 HRTIM clock cycles for input resynchronization/counter reset, followed by 3 additional cycles before the output changes.   In RM0440 Rev 9, Table 241 on page 928 lists 5–6 cycles for synchronous output response.   Figures 244–245 on page 929 instead show 6–7 cycles and no longer show the intermediate counter-reset timing.   Could you clarifyWhat is the minimum/maximum latency

Could I get the reference circuit for the STM32G474MET?

Hello,Does anyone have any information about the current availability of the STM32H573RIT6 microcontroller?I've been checking major distributors such as Mouser, DigiKey, Farnell, and TME, but this particular MCU seems to be completely unavailable.Some distributors are showing very long lead times, with expected deliveries in 2027.I'm currently designing a new device based on this MCU, and I'm concerned about its availability, especially for future production.Does anyone know why the STM32H573RIT6 is so difficult to obtain?Is this a temporary supply issue, or are there any production problems or changes planned for this specific part number?I would really appreciate any information, especially from someone at STMicroelectronics.Thank you!

Hi all,I'm designing a LoRa node with STM32WL55JCU6 (UFBGA73), using RFO_LP only (+14 dBm, high band 868 MHz). My starting point is the MB1842 reference design, which uses a BGS12SN6 RF switch between the TX and RX paths.For UFQFPN48, ST provides direct-tie reference designs without a switch (MB1789). For UFBGA73, both MB1842 and MB1849 use an RF switch, and I couldn't find a direct-tie BGA73 reference.Questions:1. Is direct-tie recommended on UFBGA73 in LP mode?2. Has anyone implemented it on BGA73? If so, what matching network did you use, and how did TX power and RX sensitivity compare to the switched design?3. Are the TX/RX impedances for UFBGA73 available to design a direct-tie network per AN5457?Thanks!

I am working on stm32 C5A3ZG platform for one of my projects. I want to use SD card for data logging. I have working SD card module. I tried to use it with nucleo_c5a3zg board using zephyr RTOS and there infrastructure of file management that code is not working on this C5 controller which uses HAL2 driver. It works on other STM32 controllers which use HAL driver.I tried to create a project in STM32CubeMX2 but couldn’t find configuration for SDMMC over SPI which would be required to interface SD card.I checked in STM example library https://dev.st.com/stm32-example-library/result?filters=N4IgpgHghgtgDgGzAOVmEAuA2gXQDQgwDGArpliAMoAqAsgMwBMAwgKwj4gBGA9lAE4ATcpxgBLQYKQB3AemyjSAEX5iAbmH4iCvAYIAKUIgGsoAc3m4Cg1Rv7UAnnEs4AvkA but was not able to find any sample or SD card.Can someone provide a sample code to me otherwise i have to look for potentially changing the platform and move to some other controller.

I laid out a 2 layer board.  It works fine but fails radiated emissions by 3 dB.  Would a 4 layer board likely reduce this enough?

Hello,I’m bringing up a custom board based on STM32MP135F and cannot read OTP reg. I am using scarthgap based Yocto distribution “openstlinux-6.6-yocto-scarthgap-mpu-v26.06.10”I modified DTS of TF-A, Optee, u-boot according to my board. File generated from openstlinux-6.1 version, I am able to able to  do read and write operation.I am able to program EMMC but not able to do OTP read and write. Getting following error on COM port-optee optee: TA_NVMEM invoke failed TEE err: ffff0006, err:0Error: OTP read issue -5dfu_read: Failed to fill bufferError Log from ST-programmer CLI-Error: Read OTP Partition failedError: Uploading the OTP structure failedError: Initializing the OTP structure failedDo I need enable any configuration or any build modification for this openstlinux-6.6?

​Hi ST Community team,Our STM32F103‑based project uses FreeRTOS integrated by STM32CubeMX, currently kernel version is V10.3.1.Questions:1. Does ST have any official roadmap / plan to update the bundled FreeRTOS kernel inside CubeMX STM32F1 software pack to a newer FreeRTOS kernel release (e.g. V10.6.x)?2. What is ST’s official recommended solution for users who want a newer FreeRTOS kernel, given CubeMX will overwrite custom‑replaced kernel sources on code regeneration?3. Are there any known compatibility constraints when manually replacing underlying FreeRTOS kernel while keeping ST’s CMSIS‑RTOS v1 wrapper unchanged?Our context:‑ Application uses almost exclusively CMSIS‑RTOS v2 APIs, very few direct native FreeRTOS calls.‑ No FreeRTOS+TCP network stack, no network‑facing interfaces.‑ Concern comes from CRA / component long‑term maintainability requirement.Thanks & best regardsAllen​

As shown on the website below, the Arc Fault Circuit Interrupter (AFCI) solution is introduced as an Edge AI use case.https://www.st.com/content/st_com/en/st-edge-ai-suite/case-studies/direct-current-arc-faults-detection.htmlFor hardware development reference, would it be possible to purchase the development board shown on the page?It would also be helpful if you could share the schematic and BOM of the PCB.