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Hello,I am working with an STM32N657 on the NUCLEO-N657X0-Q and I am trying to use the Ethernet PTP PPS signal as a hardware start trigger for TIM3.TIM3 is configured as follows: HAL_TIMEx_TISelection(&htim3, TIM_TIM3_TI1_ETH1_PPS, TIM_CHANNEL_1);sSlaveConfig.SlaveMode = TIM_SLAVEMODE_TRIGGER;sSlaveConfig.InputTrigger = TIM_TS_TI1FP1;sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_RISING;sSlaveConfig.TriggerPrescaler = TIM_TRIGGERPRESCALER_DIV1;sSlaveConfig.TriggerFilter = 0;HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig);TIM3 itself uses an external clock on ETR2 and should only be enabled by the rising edge of ETH1_PPS.The internal connection works correctly when I use the normal/fixed PPS mode.For example: ETH1->MACPPSCR = 1U;In this case the PPS rising edge reaches TIM3, TIM3->CR1.CEN becomes set, TIM3 starts counting and the rest of my application starts correctly.However, I cannot get the same internal connection to

Hi,I am working on a project using STM32H743ZITx and trying to deploy an ONNX model using X-CUBE-AI.My .ld file was doing just fine until I add the X-CUBE-AI in the middleware. It will split the BSS range across DTCMRAM and AXI‑RAM. The startup file’s BSS‑zeroing logic accesses invalid non‑hardware‑backed addresses between the two RAM regions and results in a HardFault right after Reset_Handler.My configuration is:MCU: STM32H743ZITx STM32CubeMX: 6.18.0 STM32Cube FW_H7: 1.13.0 STM32CubeIDE for Visual Studio Code: 3.9.0 Enabled X‑CUBE‑AI 10.2.1Files before and after the configuration of X-CUBE-AI are attached.

Hi all,i have a small question about Validation of a trained model.Atm i only work on PC with NEAI Studio Version 5.1.1.I used only data out of a *.csv fileI trained (benchmark) the model with around 170 Lines and 16 axis to get an accuracy of ~97%.I then validated the library with some test data with same axis count and data preparation. The learning file has the minimum amount of lines as suggested from the benchmark, i tried more lines with same result.The validation shows that even good data is treated as abnomaly so i only get an accuracy of max. 50%.Are there any hints what i am doing wrong? Many thanks in advance for answers.BR’sMartin

I am trying to generate a program a run using STM32Cube AI Studio and the STM32N6570-Dev Kit, but am running into an issue with the run failing due to a resource busy or locked (the .cproject).  Some steps I’ve already taken:Closed all other STM programs (IDE, Programmer, MX) Completely deleted and made a new project Confirmed all ST programs (IDE, Programmer, MX) are up to date by cleaning and re-installing from ST website Confirmed all ST programs are linked to the AI Studio and confirmed they’re all downloaded in their default location. Restarted my PC.Notes:I am on Windows 11, Version 10.0.26200 Build 26200 Model = ST YOLO-X Nano - Person Detection. Source: Pre-trained model from ST Model Zoo Path: stm32ai-modelzoo/object_detection/st_yoloxn/ST_pretrainedmodel_public_dataset/coco_2017_person/st_yoloxn_d033_w025_256/

Hi ST Community,I have a question while reading the reference manual RM0440.On page 915, Figure 232 shows a timing diagram where the event is labeled "Reset on CMP2". However, looking closely at the waveform, the HRTIM_CHx2 output seems to be reset at CMP4, rather than at CMP2 as the text implies.Could anyone help clarify this? Is this a typo in the manual, or is there a specific HRTIM mechanism/priority that causes the reset to actually happen at CMP4 in this scenario?Any explanations would be greatly appreciated. Thanks in advance! 

Hi, I ordered on rs-online memory M24M02E-UFMN6TP. The memory that I received has SMD marking 24M02FU (photo: https://ibb.co/gLCbX0vb). I was unable to lookup this marking on the st.com web nor in the M24M02E datasheet. The rs-online vendor also don’t know :). Can anybody verify that it’s the M24M02E, i.e. memory with the following datasheet: https://www.st.com/resource/en/datasheet/m24m02e-u.pdf ? I need 2 MBit, up to 5 ms write. IMHO the suffix 'E' distinguishes the 5 ms memories from the 10 ms and I need to be sure it’s the 5 ms version of the memory. Thanks.

Hello there,I made a project using the STM32H7A3 controller. I imported the project into my workspace and everything worked fine. The project got recognized as a CubeIDE project and compiling it was no problem. Now I wanted to switch to the STM32H755 controller which is a dual core controller. Mainly because it has an onboard ethernet connector. I wanted to test my old project on the new controller and configured a new project with CubeMX and generated Code. I set the toolchain to STM32CubeIDE and ticked “generate under root”. It generated the following structure:Now, when I import the project into my workspace, only the sub-projects CM7 and CM4 for the two cores can be separately built but the root project does not get recognized as a CubeIDE Project. Additionally, every #include for HAL driver headers has an unresolved inclusion error: main.hThis is the main.h file that got generated inside the CM7 folder. On default files and other files I copied all the includes work except for tho

When running an LCD display project, the screen fails to turn on after I cut the power and turn it back on.It only comes on when I short the NRST and GND pins.I have a 10k pull-up and a 100nF pull-down connected to the NRST pin; what should I do?

HIHow to create a project for STM32H7 with Ethernet and LwIP stack working | CommunityRx buffers labeled “Zero Copy” and are used by DMA and CPU are not marked by MPU for cacheable? only descriptors are. I couldn’t find any special clean or flush cache operations in code as well. Why is that? Image below shows only descriptors (512B) and TX (LWIP heap) are noncacheable.  

Environment: Windows 11, VS Code, STM32CubeCLT 1.22.0, stm32cube-ide-build-cmake 1.46.0, stm32-vscode-extension 3.10.0Symptom: Any CubeMX CMake project fails to configure with:CMake Error: Could not find CMAKE_ROOT !!!CMake has most likely not been installed correctly.Modules directory not found inRoot cause analysis: cube-cmake.exe is a self-contained binary embedding CMake 4.4.2, deployed at <ext>/resources/cube-cmake/win32/x86_64/. CMake's FindCMakeResourcesInInstallTree requires the executable directory to end with bin and <prefix>/share/cmake-4.4/Modules/CMake.cmake to exist. The shipped layout is neither bin-suffixed nor does it include share/cmake-4.4, and the companion cmake.exe is missing — so it fails on every run.Workaround (local): rebuilding bin/ + share/cmake-4.4/ + companion cmake.exe + a junction makes it work.Request: Please ship the full CMake resource tree (Modules/Templates) and companion cmake.exe with the extension, or have cube-cmake delegate to the C

 Does the STM32N6 XSPIM permit multiplexed mode with different memory types on the two instances? XSPIM_CR.MUXEN=1, mode = multiplexed to Port 2, with XSPI1 as MTYP=101 (HyperBus) driving a HyperRAM on NCS2, and XSPI2 as Quad SPI driving a NOR on NCS1.CubeMX 6.18 refuses it requiring both modes to be same but RM0486 reference manual makes no such distinction or state no restriction on memory types. Which one is authoritative? Can I mix them ? If mixed types are legal, are there constraints on  DQS/RWDS and CLK/NCLK when only one instance uses them (NOR does not connect to NCLK for example)?    

Hello,Since updating to 6.18.1, clicking ACCESS TO BOARD SELECTOR on the homescreen freezes STM32CubeMX permanently. The window never opens, one CPU corestays pinned at 100%, nothing is written to STM32CubeMX.log, and the processcannot be closed - it has to be killed with kill -9 / xkill. ENVIRONMENT STM32CubeMX : 6.18.1 (updater.ini: SoftVersion=MX.6.18.1, DbVersion=DB.6.0.181)Update path : 6.17.0 -> 6.18.0 -> 6.18.1OS : Ubuntu 26.04 LTS (Resolute Raccoon), x86_64, kernel 7.0.0-29-genericDesktop : KDE Plasma 6.6.5, Wayland session (app runs under XWayland)JVM : Bundled JRE, OpenJDK 21.0.10+7-LTSInstall path: ~/Documents/STM32CubeMX  STEPS TO REPRODUCE 1. Start STM32CubeMX and let startup finish.2. On the home screen, click ACCESS TO BOARD SELECTOR.3. The GUI freezes immediately and never recovers. LOGS"AWT-EventQueue-0" #46 [10722] prio=6 os_prio=0 cpu=72188.54ms elapsed=81.89s runnable java.lang.Thread.State: RUNNABLE at org.sqlite.core.NativeDB.step(Native Method)

I need more PSRAM and so went exploring and found RM0486, which seems to show that I can have two PSRAM on one XSPI port (using EXTENDMEM, §28.4.24), but I cant seem to find more than that.Is EXTENDMEM with two octal DDR PSRAMs a silicon-validated configuration on the N6 XSPI, or is it documented-but-untested territory? RM0486 notes the automatic CS switch when an access "crosses the middle boundary of the external memory". Does this work transparently with DTR memory-mapped writes and MDMA/DMA bursts, or are there alignment/burst-length restrictions at the boundary I should design around?Has anyone run 128 MB total on one N6 XSPI port? The 256 MB address window and DEVSIZE math allow it, but I'd love to hear from someone who has it working on real hardware (or from ST whether an eval/reference design exists with dual PSRAM).Anything to watch on the RIF/RISAF side for the XSPI1 memory region when all masters run secure?Board: custom using the STM32N657X0HxQ.Planned setup:Two identical

On an STM32N657X0HxQ I'm bringing up two APS51208N octal-DDR PSRAMs (512 Mb / 64 MB each, x8) on a single XSPI1 controller, XSPIM Port 1, using EXTENDMEM to get a contiguous 128 MB map. This is configured in the FSBL context.Per RM0486 §28.4.24, one XSPI drives both NCS1/NCS2 autonomously when EXTENDMEM (XSPI_DCR1 bit 21) is set.My CubeMX config (which it accepts without error):- XSPIM: Direct (XSPI1 on Port1)- XSPI1: Octo SPI, Port1 Octo, Memory Type = AP Memory, Memory Mode = Enable- Memory Size = 512 Mbit (one die, per "the size of one external memory must be set in DEVSIZE")- Chip Select Boundary = 64 MB- Memory Select = NCS1I could not find any EXTENDMEM / dual-memory / extended-memory option anywhere in the CubeMX XSPI1 panel, so I'm handling the extended-memory parts in user code. Three things I'd like confirmed:EXTENDMEM has no CubeMX exposure: is setting XSPI1->DCR1 |= (1U << 21) manually after MX_XSPI1_Init() the intended approach, or is there a CubeMX setting I've m

Hello,I have an STM32G474RE Nucleo-64 with an X-NUCLEO-IHM16M1 driving a GB2208 motor with 7 pole pairs. My goal is to use an AS5048A absolute magnetic encoder for sensored FOC and position control.MCSDK already runs the motor correctly in sensorless mode, and I can reliably read the AS5048A. However, integrating it into MCSDK has been much less straightforward than expected.Current implementationI use TIM1 CH4 to trigger TIM2. TIM2 starts the AS5048A SPI transaction approximately 3 µs after the trigger. My assumption was that this provides a relatively quiet switching interval, avoids interfering with current ADC sampling, and reduces MOSFET switching noise. I am not certain whether this assumption is valid or whether encoder acquisition should instead be synchronized with a specific PWM/ADC event.After determining the encoder direction and electrical offset, I calculate the electrical angle as:electrical_angle = (pole_pairs * mechanical_angle + electrical_offset);I then inject the en

It seems like it's been over a year since reports surfaced that the ST-Link interface isn't working on Snapdragons.Are there still no ST-Link interface drivers available for Snapdragon CPUs?

I made a linux kernel driver for VL53L9 with ~ 10 FPS.Tested on Radxa Dragon Q6A with STEVAL-VL53L9https://github.com/momoisgoodforhealth/st-vl53l9-i2c-kernel-driver

Hello everyone,It is more a bug report than a question, but in the last version of X-CUBE-EEPROM, (X-CUBE-EEPROM | Product - STMicroelectronics) I found out that value “EE_NO_PAGE_FOUND” is defined twice.Once in eeprom_emul.h:/* No page define */#define EE_NO_PAGE_FOUND ((uint32_t)0xFFFFFFFFU)And once in eeprom_emul_types.h:/** * @brief EE Status enum definition. *//* Define of the return value */typedef enum { /* External return codes : ok */ EE_OK = 0U,... /* Internal return code */ EE_NO_PAGE_FOUND, -> here, second definition EE_PAGE_NOTERASED,...} EE_Status;Is it made on purpose? Best regards

i have a problem regarding the usage of the jpeg codec on a stm32n657x0h-q to decode images. the project also involves the transfer of such images over eth0 but for the sake of isolation of the problem i have bypassed mongoose. the problem seems to relate only to jpeg interrupts since the hpdma channel0, used to feed the periperal, is working.To develop this project i followed this example for the discovery kit.doing some debugging, i noticed that confr0 is being manipulated (i used a watchpoint), both jpeg_cr and jpeg_sr are being set, but confr1 has a strange behaviour: during Init_process, its registers are properly set, then, when manually halting execution in the cycle in main, the confr1 is set to all zeros. During initialization, registers are as follows:Confr1 has DE and HDR set to 0x1, the others to 0x0;cr has JCEN, EOCIE and HPDIE set to 0x1, the others to 0x0sr has IFTF, IFNFF and COF set to 0x1, the Others to 0x0COF in jpg_cr remains 0x1, as does the JCEN, thus the pheriper

Environment: TouchGFX 4.26.0, Windows, Ruby 3.0 (bundled MinGW env). Text database: texts.xml is 13.7 MB - 20 languages x 8,255 text entries = 165,100 translations. "remap": "yes" in application.config, binary translations and binary fonts both enabled for one of the passes. Symptom: make texts took ~181s cold on a developer machine, ~2min on our build server. Adding timing markers around each phase of Generator#run put 146s of it inside StringCollector#run. Cause: the fold that collects the translations, in framework/tools/textconvert/lib/string_collector.rb:    all_strings = Array.new(languages.count, Array.new)    text_entries.each do |text_entry|      text_entry.translations.each_with_index do |translation, lang_index|        all_strings[remap_global ? 0 : lang_index] += [translation]      end    end`a += [x]` allocates a new array and copies the whole accumulated contents on every iteration, so this is O(n^2) in the number of translations. With global remapping every language fold

Hi everyone,I am using an STM32H753ZIT6 on our custom PCB. Before this, I was successfully programming the STM32H753ZI on the NUCLEO-H753ZI board using the UART bootloader (system memory boot mode) with STM32CubeProgrammer and a USB-to-UART TTL converter. I have never used an ST-LINK for programming.I followed the same hardware connections and programming procedure on our custom PCB, but STM32CubeProgrammer always returns a timeout error and cannot connect to the MCU.Setup MCU: STM32H753ZIT6 Software: STM32CubeProgrammer Programming interface: UART bootloader (not ST-LINK) USB-to-UART converter connected to USART1 TX of USB-UART → STM32 PB15 (USART1_RX) RX of USB-UART → STM32 PA9 (USART1_TX) Manual boot mode selected (not using RTS/DTR auto boot) Programming Procedure Hold BOOT0 HIGH. Reset or power-cycle the board. Release RESET while keeping BOOT0 HIGH. Click Connect in STM32CubeProgrammer. This exact procedure works on the NUCLEO-H753ZI but fails on our custom PCB.

Hello ST Team,Good morning!I am currently working on integrating the VL53L9 sensor with the STM32N6570-DK development board. I have successfully obtained the STSW-IMG053 software package, which is designed for the STEVAL-VL53L9 evaluation board using the MIPI CSI interface.However, my target hardware configuration is different. My objective is to use the following setup:Software Package: STSW-IMG053 Host Board: STM32N6570-DK Sensor Board: X-NUCLEO-53L9A1 Communication Interface: I3CI would like to port the STSW-IMG053 software package to support the X-NUCLEO-53L9A1 evaluation board while retaining the STM32N6570-DK as the host platform.I would appreciate your guidance on the following points:Is there an official procedure or application note describing how to port STSW-IMG053 from the STEVAL-VL53L9 (MIPI CSI) platform to the X-NUCLEO-53L9A1 (I3C) platform? Are there any reference projects, example applications, or software packages available for the STM32N6570-DK with the X-NUCLEO-53L9

**VL53L8CX ranging stops after a few frames (2-4 typical, up to 28 seen once) clean status, no error on three independently-built boards****Setup:** Custom board, VL53L8CX (I2C mode) + STM32G0B1KBU6 host MCU, ULD driver, 4x4 resolution, 10Hz continuous ranging mode, 30ms integration time. **Symptom:** `vl53l8cx_init()` and `vl53l8cx_start_ranging()` both succeed. Ranging produces good frames (plausible per-zone status/distance data) for a small number of frames usually 2-4, occasionally more (saw 28 once) then `check_data_ready()` starts returning `VL53L8CX_STATUS_OK` with `data_ready` staying false indefinitely. No error code in the common case. I2C bus itself stays healthy throughout (clean ACKs on every transaction, confirmed via logic analyzer).**One-off exception:** on a single occurrence, `check_data_ready()` returned `0x84` instead of `0x00`. I found the earlier thread here (linking below) where a `0x81`/`0xC5`/`0xCA`-style status was identified as a GO2 (internal MCU) error. I

Hello STM team,   We are working to interface the  NUCLEO-U5A5ZJ-Q and nRF7002-DK using QSPI. We are using vanillas zephyr. We are able to built the code for SPI. But can not be able to built for QSPI. It will be very helpful if you provide a proper support to interface this.

I’m trying to Generate 4 PWM for my rectifier circuit so my right leg is of tim1 ch1 and tim1ch1N and my left leg  is of tim1ch2 and tim2ch1N , what i want to achieve is i want 50% duty with phase shift between my leg1 and leg2 i saw many examples with OC mode , with different timers but i need it in the same tim1 only this are my pin outs