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When calling HAL_QSPI_Abort() to disable memory mapped mode, with the memmap timeout active, I find that there is a race condition that can cause the abort to fail when it should not. If the memmap timeout happens after the abort function's check of the busy flag, but before it can write to the abort bit, the TC flag will never be set and the abort function will wait for the configured qspi timeout, then return an error.I am testing this on a STM32F769I-DISCO board.I have found that the following patch will fix the issue: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c index 8404466..01a06ca 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c @@ -2381,19 +2381,19 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABOR

Dear Community,we are writing to report a behaviour observed on the STM32WB5MMG module, and to submit a modification we applied, asking for your assessment of its correctness.Some context on why this matters to us: the product is a battery-powered device, and a primary design goal is to minimise power consumption, hence to maximise the time spent in Stop2. Every exit from Stop2 carries a fixed cost — clock restoration, external oscillator start-up, peripheral re-enabling — which we pay in full even when the wake-up has nothing to do. This is why waking once per second, on a device whose nearest application deadline is tens of seconds away, is a concrete problem for us rather than a cosmetic one.ConfigurationFreeRTOS V10.3.1 in tickless idle (configUSE_TICKLESS_IDLE = 2), tick rate 1000 Hz Low power mode Stop2, CFG_LPM_SUPPORTED = 1 Wake-up from Stop2 through the RTC Wakeup Timer, driven by your HW Timer Server (hw_timerserver.c), as in the BLE_HeartRateFreeRTOS example LSE at 32774 Hz;

We are seeing different SRAM2a availability between STM32WB15CC devices with different silicon/FUS revisions.On our older STM32WB15CC devices (silicon Rev B), the device has FUS version 1.2.2.0. On these devices, BRSD_A is set, so the complete 32 KB SRAM2a region (0x20030000–0x20037FFF) is non-secure and available to CPU1.On newer STM32WB15CC devices (silicon Rev Z), we see FUS version 2.2.0.1. On these devices, the relevant configuration is:BRSD_A = 0 SBRSA_A = 0x1A Secure SRAM2a therefore starts at 0x20036800 SFSA = 0x8C, corresponding to 0x08046000 SBR = 0x1180As a result, only 26 KB of SRAM2a (0x20030000–0x200367FF) appears to be available to CPU1, while the upper 6 KB is secure.There is no wireless stack installed, and our application does not use the wireless stack/CPU2 functionality.Our existing production firmware requires the full 32 KB SRAM2a. Reducing the linker region to 26 KB is therefore not a viable workaround.This has become a production-critical issue for us: our exist

Hi, Good day.This is the third party programming manufacturer.We are searching out the programming guide of SR5E1E570C30F01X because our customer requires this series for programming, and they will use our programming handler for production. Now, We need these matirals for progarmming development.Keil C PACK file and sample code (I didn’t see it in Keil website) The programming guide for SR5E1E570C30F01X includes commands and flow and related information about programming.Please let me know if need to sign NDA.Thank you.Jack 

For STM32C562RE, why can CubeProgrammer validate the OEM key and report "RDP2 unlocked successfully", while the RDP regression does not erase the existing user flash and flash erase remains prohibited? Is this a known CubeProgrammer/ST-LINK limitation or does this indicate that the device was provisioned with a non-regressible security configuration?Device: STM32C562RETx / NUCLEO-C562RECubeProgrammer: v2.22.0ST-LINK: V3J17M11SWD connection works.Device ID: 0x44E.OEM key is available.RDP unlock operation sometimes reports:"Validation Status: 3"followed by:"RDP2 unlocked successfully"After physical power removal and restoration:RDP_level = 0xFF (Unknown Value)Flash still contains:0x08000000 : 200007C8 08000671 0800073D 08000735Mass erase:Error: Mass erase operation failed. Please verify flash protectionProgramming:Erasing internal memory sector 0Error: failed to erase memory

Heyho,I’m confused - or the STM32G431KBU (in QFN32) is…I’m using ADC 1 with 2 external inputs, PA0, PA1, and the internal “REFI” and temperature channel “TEMP”.All running with continuous and circular DMA in the background, no interrupts. If I need an ADC value, I simply grab it from the ADC DMA buffer.This is basically working, except for the channel sequence. Which I set manually, but have at least triple-checked the SQR1 / SQR2 values with the RM... If I set up the channel sequence in ADC1->SQR1 in the order: PA0, PA1, REFI, TEMP, then I find in the DMA buffer instead of this order: 0, PA0, REFI, TEMP→ so PA0 was “shifted”, PA1 is nowhere to be found (it is not 0, checked the GPIO via scope). If I add and insert a dummy channel “VDMY” as the first in the sequence, so that the sequence should result in VDMY, PA0, PA1, REFI, TEMP, I find this order in the DMA buffer:PA1, VDMY, PA0, REFI, TEMPAt least I get all the channels now, the measurement data is correct. So, what am I messing

Hi,I want to start a custom board design using STM32F405 but later I want to upgrade to STM32F407.Below are the features I want to target.Ethernet (IEEE802.3, TCP/IP< DHCP, MAC, SNTP) Can ethernet (10/100) over SPI interface (W5500) will work for STM32F405?  USB OTG HOST UART x3 Analog 12-16 bit PWM input: at least 10KHz 8-bit Parallel interface for display.Is there any development platform available to cater all these features.Also, please suggest the programming tool as well for production.Let me know if you have any questions.Thanks, Mukesh

I am using the STM32F746NGH6 controller in my circuit to read external ADC (16bits) and transmits the same through USB. I have configured USB in OTG FS (device) MODE including AUTO detection.  Test Set-Up.The USB is always connected and controller is powered on for testing and powered off after testing is completed Earlier observationThis was practiced for about two months and was working ok without any issues Current observationThe same is not able to recognize USB (i.e. auto detection is not happening) Further Analysis 1) On probing the circuit, it was observed that 3V is present at USB V-Bus line always after the board is power on, even without the USB cable connected  Please clarify does it cause the issues. If yes, why and how Queries We would like you to clarify the following points about the user operation sequence1)    Be the controller power on, when engaging and disengaging USB cable2)    There is no need for any sequencing in user operation NOTE:We are in need of fix to avoi

Hello, I'm looking for a bsdl file of SPC58NH92C5 device, could you please send me one if available? Thank you in advance!:)

Hi All,We are developing a BMS application using the SPC560B50L1 microcontroller with SPC5 Studio, and need help with two topics:1) Low-Power Mode Wakeup via PA4 (WKPU9)We want to put the SPC560B50L1 into a low-power mode (STOP/STANDBY) and wake it up using pin PA4, which maps to WKPU channel 9 as per the SPC560Bxx Reference Manual (RM0017, Table 96 - Wakeup Vector Mapping).However, in SPC5 Studio, under "SPC560BCxx Low Level Drivers Component RLA" -> "Enabled Drivers", there is no dedicated WKPU driver option available (unlike some other device families, e.g. SPC582Bxx, which do expose a WKPU checkbox).Could someone please help with:- The correct/recommended way to configure WKPU9 (PA4) as a system wakeup source on SPC560B50L1 within SPC5 Studio- Any example project or reference code demonstrating:  a) EIRQ/WKPU channel configuration for a specific pin  b) Enabling system wakeup capability (WRER register or equivalent) so the configured pin can wake the MCU from STOP/STANDBY mode 

can you advise if there is a ref design for the STWLC38?  

STSW-WPSTUDIO is not on ST.com and the links to Github dont exist anymore. How do I upload firmware on the STWBC86JR? And where can I get the firmware that needs to be uploaded? 

Hello ST Community,I am working with an STM32H7S78-DK board and trying to perform Debug Authentication using STM32CubeProgrammer v2.21.0.The Discovery sequence succeeds successfully, and the target is detected correctly. However, the Debug Authentication fails after selecting the required permission.EnvironmentBoard: STM32H7S78-DK STM32CubeProgrammer: v2.21.0 SDM Library: v1.2.0 SDA version: 2.0.0 PSA lifecycle: ST_LIFECYCLE_CLOSED PSA authentication version: 1.0 Cryptosystem: Ecdsa-P256 SHA256 Key: Keys/key_3_leaf.pem Certificate: Certificates/cert_leaf_chain.b64 Password: Binary/password.binDiscovery resultThe discovery command completes successfully      -------------------------------------------------------------------                       STM32CubeProgrammer v2.21.0      -------------------------------------------------------------------Start Debug Authentication SequenceOpen SDM LibSDMOpen                       :   624 : open       : SDM API v1.0SDMOpen                       :

We are planning to use the 30 W Wireless Power Receiver IC (P/N: STWLC89JRO) in our product and would appreciate your support in providing the following information at the earliest:Technical Datasheet Design Guide / Reference Design Documents

We are a large electronics company that has been collaborating with ST for over a dozen years.We are currently designing a wireless charger for one of our automotive clients and plan to launch mass production within a few months. Unfortunately, we are unable to test the hardware we have designed because we cannot obtain the necessary STSW-WBC2STUDIO software.Please provide access to STSW-WBC2STUDIO.Thank you in advance for your prompt assistance.Best Regards

I had like to understand the recommended BMS configuration at the architecture level for both my current and future battery configurations.1. 2S buildCell monitoring Passive cell balancing Battery protection SOC / SOH estimation Battery current measurement Pack/cell voltage measurement Battery charging Temperature monitoring2. 7S build(future scalable)Same functional requirements as above Preferably using an architecture that can scale from 2S to 7S with minimum changes to the overall systemIt would be particularly helpful if you could provide, for each configuration:Recommended cell-monitor/BMS IC Recommended protection IC Recommended charger IC Recommended current/voltage measurement approach Recommended SOC/SOH approach Recommended cell-balancing method and typical balancing current Whether you would use internal or external balancing FETs/resistors Any additional ICs/components you would normally consider essentialI’m mainly looking for a practical, industry-proven architecture rat

Tool versions (let me know if more details are needed on this):Zephyr RTOS  v4.4.0STEdgeAI Core V4.0.0ST Edge AI Core v4.0.0-20500 359356bb0 STM32CubeAI 12.0.0-RC4Board: Nucleo N657X0 Q (nucelo_n657x0_q from Zephyr RTOS boards configuration) I generated NPU deployable code from the int8 quantized CNN model using this command:stedgeai analyze -m ./CNN_int8.onnx --type onnx --target stm32n6 --st-neural-art I tried to integrate the generated code in the zephyr environment for deployment. But the application fails when the calls to read the weight from external flash is requested using the APIs.The application is such that there are certain things running in the MCU after which the NN code is called using teh generated code from STEdgeAI Core tool and quantized CNN model. Succeeded calls (successful calls from the network code):LL_ATON_DECLARE_NAMED_NN_INSTANCE_AND_INTERFACELL_ATON_RT_Reset_NetworkLL_ATON_Input_Buffers_Info_networkLL_ATON_Output_Buffers_Info_networkLL_Buffer_addr_start  

Hello ST team,  Could you please provide the steval-wbc2tx70 & STWBC2-HP documentation.

Hi,support     Can you provide me with the schematic for the steval-wbc2tx70 and more register information for the STWBC2-HP chip?Than

Dear Mr./Ms.:I have downloaded StellarStudio and installed it in win10 OS.I followed quick_start_guide.pdf, and try to build the demo code​ included in StellarStudio.“make all” will reports errors.would you pls give me some guidance.Thx a lot.BR.Hawk.

Hi all,I'm trying to get the PLS UDE Starterkit debugger working with the SPC56B-Discovery board (SPC560B54L5) and consistently hit the same error on every connection attempt:PpcJtagTargIntf: Can't connect target!PpcJtagTargIntf: Failed to open communication channel!FtdiCommDev: Failed to open FTDI device driver!Setup:- SPC5 Studio 6.0 + HighTec GCC, project builds clean (0 errors)- PLS UDE Starterkit 2021.05, correct target config (stm_spc560b54_bolero_discovery_starterkit_debug_jtag.cfg)- Board shows correctly in Device Manager as "PLS USB JTAG Adapter for SPC5xxx A/B", VID_263D PID_4001, no driver warnings- Reinstalled the driver using the bundled InstallPlsUsbJtagDriver script- Ran UDE as Administrator, tried multiple USB ports, full system restartDespite all of this, the error is 100% reproducible — every attempt, exact same message. Sometimes the device also disappears from Device Manager right after a failed attempt.Has anyone run into this exact combination before? Open to tryi

I found an issue while using STM32F051, and the background is that I want to generate an interrupt when the host receives a CRC error, in order to perform my error handling in the interrupt handler. But when a CRC error occurred, the CPU did not jump into the interrupt service function. At this point, I checked that the CRCERR flag was raised and the ERRIE interrupt enable was also enabled. I have tried other conditions that can trigger error flags to generate interrupts, such as OVR, FRE, MODF, etc. These flag bits can generate interrupts and enter the interrupt service function, which proves that my interrupt enable steps are correct. I carefully reviewed the manual again, and it clearly states that when ERRIE is set, CRCERR can trigger an interrupt. So I want to know if there are some hardware defects that did not connect the CRCERR signal to the NVIC.

In this case, I want to debug a new control board whose MCU is STM32H563. But I didn’t have a proper debugger, so I want to use the ST-LINK debugger of the STM32H5 Nucleo-144 board for the new board’s debugging.The debugger connector of the STM32H5 Nucleo-144 board : The debugger connector of my own board : I want to connect the 2 connectors through a cable for the external board’s debugging.So currently my issue is that the ST-LINK debugger can’t be used on the external board, I tried some methods for this, but it didn’t work, such as removing the jumper of JP5, connecting the jumper for JP1. My question is that : Can the ST-LINK debugger of STM32H5 Nucleo-144 board be used on an external board, if possible please show me the steps of the configurations on the Nucleo board.

Hi, I'm new to PCB design. I'm planning to build a handmade board for a project that uses the STM32F103C8T6, and I've run into some issues in certain parts of the PCB design. My board only has copper on one side (single-sided). For the HSE 8MHz and LSE 32.768kHz crystal oscillators, the body needs to be placed on the bottom layer, with the pins passing through holes to reach the top layer where they will be soldered. I'm concerned about the soldered area where the solder forms a fillet on the top layer, and whether this fillet, being in line with the OSC traces running toward the MCU, could cause problems. To put it simply: could the solder fillet of the crystal on the top layer cause frequency issues, reduced performance, or make it completely unusable? Since my project is currently in the experimental stage, I haven't built the board yet. The images I've included are just for better understanding and were collected from a few websites. What's your opinion on this?

Could you share the schematic file for checking the pin out for this two programmer - STLINK-V3MINIE, ST-LINK/V2-ISOL