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UL have requested CDRH certificate for VL53L8CX. Can anyone help?

Hello, I have an ST Nucleo U5A5ZJ-Q board. I am powering the board through the CN1 connector and using the ST-LINK at the same time.In the project I am working on, I would like to connect a USB device to the hardware. For this purpose, I want to use the USB Type-C connector.When I connect the sensor to the Type-C connector, it does not receive any power. My assumption is that I cannot power the device through the USB Type-C connector. Also, LD7 does not light up.I wanted to consult you about this before doing anything that might damage the board.In addition I use usb standalone(STM32Cube FW_U5 V1.8.0).Thank you in advance for your support. Best Regards,Faruk

I am using EVLSPIN32G4-ACT. Am I correct to assume that if I want to use external resistors R16,19,23,26,29 & 32, I will have to connect TP3,4&5 to GPIO1_EX, GPIO2_EX & GPIO3_EX on CON6, as this is the only way I can connect the op-amp outputs to ADC inputs?

Hi, i am using the TCPP03-M20 for the first time. This device is stand alone. i have the device setup for 5V, which is all that is required. there is no power to the device initially when connected to the USB-C port. CC1c and CC2c pins are at around 1.65V. i do not see any voltage on Vbus. have attached the schematic section for this circuit. .If i apply 3.3v to Vcc_Vconn VBUS is still 0V. Any help appreciated. Mark

i can't get to download stm32cubeide. download jus

Introduction:Hello ST Team and Community, Following a recent architectural discussion on the Zephyr RTOS project (recommended by @erwango to be shared here), I would like to submit feedback and a feature proposal regarding how the Flexible Memory Controller (FMC) master controller enable gate is handled in the STM32Cube HAL/LL drivers.Background: On newer STM32 architectures (STM32H7, STM32U5, STM32H5, STM32H7RS, STM32N6, STM32MP1/2), the FMC block contains a master peripheral gate bit (FMC_BCR1_FMCEN or FMC_CFGR_FMCEN) which must be asserted for external bus transactions to occur. Currently in the STM32Cube firmware:There is no standalone HAL_FMC_Init() or public LL_FMC_Enable() API.The master gate is only asserted  via the private macro __FMC_ENABLE() inside:  HAL_SRAM_Init()  HAL_SDRAM_Init()  HAL_NOR_Init()  Inversion of responsibility: While this chip-centric approach works seamlessly in standard STM32CubeMX bare-metal projects with discrete SRAM/SDRAM chips, it creates architectu

Hello,I ran into a bug in fx_stm32_sd_driver function.Our firmware was calling fx_media_volume_set on a partitioned card and we found it was corrupting the disk. The issue is  that the FX_DRIVER_BOOT_WRITE case statement hardcodes the boot sector to be at sector number 0. This works for unpartitioned (superfloppy) layouts, but does not work on partitioned SD cards with a master boot record. Calling fx_media_volume_set on a partitioned drive overwrites the MBR instead of the boot sector and corrupts the disk.Note that the FX_DRIVER_BOOT_READ, which also has to manage this problem correctly calculates the offset using the _fx_partition_offset_calculate function.Regards,Mike

Hi everyone,I am currently working on a project using an STM32H533RET6 and I need to implement an RS485 Slave interface. To save as many GPIOs as possible, I was wondering if it is possible to use just one single CPU pin for both USART TX and RX (and one additional pin for both RE and DE)?I know that the STM32 supports a Single-wire Half-duplex mode (setting HDSEL in the USART_CR3 register). From my understanding, this makes the TX pin bidirectional and completely frees up the RX pin to be used as a standard GPIO.However, my main concern is how to connect this to the external RS485 transceiver. A standard transceiver (like the MAX485) requires at least three pins: DI, RO, and the DE/RE control pin.My thoughts so far: If I tie DI and RO together and connect them to the STM32's TX pin, I would still need a second GPIO to toggle the DE/RE pin. That would be a 2-pin solution.Has anyone successfully implemented this approach in a real project? Are there any hidden pitfalls regarding the con

Hi,I am using my own board based on an STM32F207ZG and STM32F2 HAL v1.9.4.I implemented an HID Host using STM32CubeIDE (v1.19.0), simply selecting USB Host and HID class support in CubeMX and generating the code.I was able to read key events from a standard USB desktop keyboard. However, I was not able to read any key events from a USB HID RF tag reader.While debugging usbh_hid.c, I noticed the following:    USBH_HID_SetProtocol(phost, 0U); generates a SET_PROTOCOL request with wValue = 0x0001  (Report Protocol)whereas:    USBH_HID_SetProtocol(phost, 1U); generates wValue = 0x0000  (Boot Protocol).because this implementation:if (protocol){ phost->Control.setup.b.wValue.w = 0U;}else{ phost->Control.setup.b.wValue.w = 1U;}In other words, the protocol parameter passed to USBH_HID_SetProtocol() is inverted with respect to the value actually transmitted in the USB SET_PROTOCOL request URB.I noticed that the same implementation is still present in STM32F2 HAL v1.9.6.I am not sayi

Part: STM32U375CE (Cortex-M33 r0p4), ChibiOS, system clock MSIS 4 MHz, FLASH_ACR = 0x100 (0 WS, prefetch on), ICACHE enabled, LDO. Firmware enters Standby from a small function: PWR_CR1.LPMS = 100b, SCB_SCR.SLEEPDEEP = 1, DSB, ISB, WFI. Standby exit is by reset, as documented. Symptom. With identical source, whether the part enters Standby depends on where code lands in the image. Inserting n nops into a function that is not even on the idle path flips idle current between 4.4 uA and 1040 uA (0/2 nops sleep; 4/8/16/32 stall; three trials each). Two builds with a byte-identical 77-instruction arming function, same WFI offset within its flash line, same call list, differing only in two literal-pool data words, behave differently. Whole-tree -O0 always sleeps. Disabling ICACHE, or running the arming sequence from SRAM (.ramtext), makes every build stall. What the stalled state is. Plain stores into retained SRAM2 (PWR_CR1.RRSB3) read back over SWD after connect-under-reset show the firmwa

Hi all,I’m configuring a GitHub Actions CI pipeline for an STM32 project with auto-generated CMake files (STM32CubeIDE/CubeMX).I already created a custom Debian container including the dedicated ARM toolchain (arm-none-eabi) version 14.3.rel1 for reproducible builds.What is the best practice: how do I have to configure the CmakeList? Is there a template?How can I keep custom flags/include paths/post-build steps without editing generated files directly?Do you have a minimal working example for STM32 + CMake on GitHub Actions (including .elf/.bin/.hex artifacts)?Thanks in advance for any recommendations.

I am using the STM32F405RGT6 built-in System Memory CAN bootloader for firmware update.Configuration:MCU: STM32F405RGT6 CAN: CAN2 (PB5 RX / PB13 TX) External HSE: 24 MHz CAN bitrate: 125 kbps Host: Jetson Linux / SocketCAN Standard 11-bit CAN IDI am facing an issue with the CAN Erase command (0x43).For example, to erase Sector 8:cansend can0 043#08The STM32 responds with the first ACK:043 [1] 79but I never receive the second/final ACK after the erase operation.So the sequence is: Jetson -> 043#08STM32 -> 79 <-- received <-- final 79 is NOT receivedImportant observations:Mass erase using 043#FF works. Individual sector erase using STM32CubeProgrammer + ST-Link/SWD works, including Sector 8. RDP = AA (Level 0). WRP0–WRP11 are unprotected. Sector 8 address is 0x08080000. CAN communication with the ROM bootloader otherwise works.Therefore, it appears that the 0x43 command is being accepted by the ROM bootloader, but the sector erase operation doe

Hi everyone,I am currently working on repairing my NUCLEO-F767ZI board (Revision: [MB1137 Rev B]). The 3.3V LDO regulator (U6) was damaged and needs to be replaced.While working on it, I found a hardware discrepancy: According to the official schematic, U6 is specified as LD39050PU33R (a 6-pin DFN package). However, on my physical board, the PCB footprint for U6 clearly has 8 pads. The damaged original IC I removed is an 8-pin package with the marking code "PH 2kE". Since a 6-pin IC cannot fit on this 8-pin footprint, has anyone encountered this before? Could you please help me identify the correct 8-pin LDO part number to replace it?I have attached pictures of the physical 8-pin IC and the 8-pad PCB footprint for reference.Any advice would be greatly appreciated. Thanks in advance! Figure 1: The removed original 8-pin LDO IC with the marking code "PH 2kE".Figure 2: The physical 8-pad PCB footprint for U6 on the NUCLEO-F767ZI board. 

So I have an STM32 project in VSC and when I first set up this project and started debugging, I vaguely remember being asked by VSC to create a launch.json file.Now it seems I can build a ‘debug’ session, and launch it, and debug with all the usual features like step-in, step-out, continue, and so on. But how do I now add a ‘release’ build, which strips debug info and allows me to program a device without debugging it? [I am trying to be a good citizen and get along with STM32 for VSC, but so far it seems like i) A retrograde step ii)A mix of modern UI’s and very old looking Java (MX) and iii)You need a science degree in CMAKE to understand anything. ]My launch.json looks like this:{ // Use IntelliSense to learn about possible attributes. // Hover to view descriptions of existing attributes. // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 "version": "0.2.0", "configurations": [ { "type": "stlinkgdbtarget", "requ

 OverviewThis chapter introduces how to use the on-chip DAC of the STM32C5 to generate a fixed analog voltage output. The STM32C5 DAC supports 12-bit/8-bit resolution, external pin output, output buffering, and DMA. In 12-bit mode, the digital input range is 0 to 4095.In this experiment, DAC1 Channel 1 is used, with the analog voltage output through PA4 (DAC1_OUT1). The program calculates the DAC digital value according to the reference voltage and the target output voltage, sets the conversion data using HAL_DAC_SetChannelData(), and then starts the DAC output using HAL_DAC_StartChannel().  Hardware PreparationFirst, prepare a development board. In this example, I use a self-designed development board. Samples can be requested if needed.The main MCU is STM32C542CCT6.     Reference CodeGitHub:https://github.com/CoreMaker-lab/STM32C542_SENSOR  Creating a Project with STM32CubeMX2In this example, STM32CubeMX2 is used to generate the project, with STM32C542CCT6 selected as the target MCU.

Kindly provide an example code to make my steval esc001v1 to a working ESC for a drone i have configured PA15 as input which accept PWM signal but throttle mapping is not done any help will be appreciated. 

Hi,We have observation that STM32L496RGT6 takes around 32mA current when not even flashed first time. That is STM32 has purchased from supplier and assembled only. It takes 32mA. When it is first time programmed when it takes less current.What could be reason and how to solve first problem./Anurag 

Hi,I'm measuring the power consumption of the LIS2DUXS12 for FSM, MLC, and the step counter with or without Smart Power mode (SMART_POWER_EN bit in CTRL1). The current reduction matches my expectations (e.g. ~13.3 µA down to ~8.2 µA with 1 FSM program running). AN5909 describes the mechanism as dynamically scaling the supply current of the embedded function hardware blocks between "operating level" and "lower non-operating level".My question: Is there any trade-off to enabling Smart Power mode besides the current savings? For example:Any added latency? Any impact on accuracy? Any recommended ODR for Smart Power? Any settling time when switching between operating and non-operating levels?I couldn't find this addressed in the AN5909 or the datasheet, and I haven't found any existing thread relating to this. Any clarification would be appreciated.Thanks!

Hello ST Expert,We have been experiencing a number of shorts and opens on the IIS2DLPC and suspect issues with our solder mask layer. We have tried opening the solder mask under the component and have tried leaving the solder mask under the component, please see images below.  We have experienced shorts and opens using both of these methods. Could you please provide the recommended solder mask layer for this component? Thanks, Sam 

Is there ST-Link V2 driver for Windows 11? I am using Microsoft Surface Pro + Copilot and trying to load code on STM32L476.

I am developing a custom embedded device that uses PIMA with USBX in order to access the SD card contents of my PCB from a PC through USB.When UX_PIMA_WITH_MTP_SUPPORT is enabled, the device is correctly detected by Windows and communication works properly.However, in order to correctly represent a hierarchical folder structure in Windows Explorer using MTP, I would need support for command 0x9805 (GetObjPropList, CMD 00000043). As far as I can see, USBX does not implement this command.To avoid implementing the full MTP property system myself, I wanted to use the more generic PIMA behavior instead, where the host requests ObjectHandles each time the user enters a folder, similar to how old digital cameras behaved.The issue is that when I disable UX_PIMA_WITH_MTP_SUPPORT, the PC no longer even recognizes that a USB device is connected. If I enable the macro again, everything works correctly.So my question is:Is disabling UX_PIMA_WITH_MTP_SUPPORT expected to completely break USB enumerat

Hi, STNow for my STEVAL-MKI225A Board which contains LPS28DFW Barometer sensor I Used the application “read_data_polling.c” which is running on “NUCLEO-F401RE Board” to test the sensor with the default example configurations which are:md.odr = LPS28DFW_4Hz;md.avg = LPS28DFW_16_AVG;md.lpf = LPS28DFW_LPF_ODR_DIV_4;md.fs = LPS28DFW_1260hPa;and I noticed that when I’m getting the data in the while loop, It works correctly only with I2C Standard Mode (100KHz) and it stucks with fast mode.but the main problem is when I’m adding delay or another code execution to the while loop, It also stucks and doesn’t work unless I removed the delay or the code added. 

Hi, We are using PCB coil antenna. We need your support to tune the filter circuit.Thanks,Sankar.K

Good afternoon, We are currently working on the development of a board intended for use in explosive areas. For the design calculations, could you please confirm the junction-to-ambient thermal resistance (θJA) of the LSM6DSV80XTR? In the Datasheet it is not avaliable.

LL_ATON_LIB_Concat falls back to 4× memcpy when the concat axis is not leftmost — 32% of a 4 ms real-time budget on STM32N6Hardware: NUCLEO-N657X0-Q (STM32N657X0H3Q), Cortex-M55 @ 800 MHz, Neural-ART. Tools: ST Edge AI Core 4.0, STM32Cube_FW_N6 V1.4.0, STM32CubeIDE 2.1.1. Application: real-time audio, hop = 192 samples @ 48 kHz = 4 ms = 3.2 M cycles, hard deadline, underrun must stay 0.1. Concat falls back to a byte loop, and it is one third of the budgetOur graph is a streaming TCN (int8, L=12, C=88, T=48) run per audio hop with two voices, so the tensor layout has the voice axis leftmost: [C][V][T]. The graph contains 12 Concat blocks (channel-wise taps).Epoch profiling (LL_ATON_EB_DBG_INFO, DWT cycle counter on the M55) showed those 12 blocks costing 1 019 501 cycles per inference — 32% of our entire 4 ms budget. No compiler option changed the number.The cause is in the runtime source: LL_ATON_LIB_Concat takes its fast DMA path only when the concatenation axis is the leftmost signif