Product forums

Hello, I’m working of a TM32F769 board the content of the 4 KB backup SRAM (BKPSRAM,0x40024000) is lost after a hard power cycle (VDD removed and re-applied),although:  - VBAT is supplied by a 3 V lithium coin cell (Renata, CR1225-type),  - the backup regulator is enabled (PWR_CSR1.BRE = 1) and ready    (PWR_CSR1.BRR = 1) before power-off, and BRE is still set at the next    cold boot,  - the rest of the backup domain is retained: RCC_BDCR keeps its value    (LSE on/ready, RTCSEL = LSE, RTCEN = 1) and the RTC keeps running,  - HAL_PWREx_EnableBkUpReg() returns HAL_OK,  - BKPSRAM content IS retained across system resets (NRST / IWDG) while    VDD stays present. The test I have performed: 1. Flash and run the firmware once (writes 0xDEADBEEF to BKPSRAM word 0). 2. Disconnect the ST-LINK cable from the board (to avoid back-powering    through SWD pins). 3. Remove all board power (VDD). The coin cell stays connected to VBAT. 4. Wait for 5 min. 5. Power the board up without the debugger and

Hi, could you please check the colored cell highlighting in RM0511 Rev 6 register map tables?For example, page 304 states "The green cells indicates the register is in the VDD12o power domain" but no green cells are visible.This affects at least Table 38 (LCSC register map, p. 304).RM0511 Rev 5 displays the colors correctly on the equivalent pages.Thanks

at stm32wl33 datasheet there is RX sensitivity topic but i think wrong– RX sensitivity @ 1% BER:◦ -132 dBm @300 bit/s 433 MHz OOK◦ -128 dBm @300 bit/s 868 MHz 2(G)FSK◦ -112 dBm @38.4 bit/s 868 MHz 2(G)FSKit should be kbit/s .  

In Section 5.1 of datasheet for VL53L9CX, it says “Refer to the postprocessing technical note (TN1596) for more details of the data formatting, processing, andfilter functions.”But I cant seem to find the TN1596 document. I am looking for information on the distortion correction on the raw depth output.

Hello,I’ve migrated from sdk V25.06.11 to sdk V26.06.10 to compile FIP, tfa, boot and kernel for STM32MP257F-DK board.While the scripts “make_mp2_FIP.sh” and “make_mp2_KERNEL.sh” were working properly with sdk V25.06.11, the script “make_mp2_FIP.sh” hangs nows in the middle of the compilation with an error “ LDS     /Documents/STM32_packages/Sources_v26.06.10/stm32mp-openstlinux-6.6-yocto-scarthgap-mpu-v26.06.10/sources/ostl-linux/tf-a-stm32mp-v2.10.24-stm32mp-r3.1-r0/tf-a-stm32mp-v2.10.24-stm32mp-r3.1/../build/optee-sdcard-stm32mp257f-test2-mx/stm32mp2-stm32mp257f-test2-mx.o/opt/st/stm32mp2/5.0.17-openstlinux-6.6-yocto-scarthgap-mpu-v26.06.10/sysroots/x86_64-ostl_sdk-linux/usr/libexec/aarch64-ostl-linux/gcc/aarch64-ostl-linux/13.4.0/ld: cannot find -lgcc: No such file or directory/opt/st/stm32mp2/5.0.17-openstlinux-6.6-yocto-scarthgap-mpu-v26.06.10/sysroots/x86_64-ostl_sdk-linux/usr/libexec/aarch64-ostl-linux/gcc/aarch64-ostl-linux/13.4.0/ld: cannot find -lgcc_s: No such file or direc

In RM0490 Rev 6, Reference Manual for the STM32C0, the ADC Software Calibration Process is specified as follows: Software calibration procedure1. Ensure that ADEN = 0, AUTOFF = 0, ADVREGEN = 1, and DMAEN = 0.2. Set ADCAL = 1.3. Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if theinterrupt is enabled by setting the EOCALIE bit in the ADC_IER register.4. The calibration factor minus one can then be read from bits 6:0 of the ADC_DR orADC_CALFACT registers. The resulting calibration factor must be incremented by oneand written back to the ADC_CALFACT register.5. To reduce the noise effect of the calibration factor extraction, the software can makethe average of eight calibration factor values. This step is optional but recommendedfor better accuracy.The averaging procedure is as followsa) Obtain eight incremented calibration factor values (perform eight times step 2 tostep 4).b) Calculate the average of these eight values and round it up to the nearest integer

Hi All,Ok new to SPCSudio and currently using version 6 - have big problems with components  inparticular  PAL.Basically all the tutorial talk about using PAL to flash an LED or toggle a GPIO pin.But version 6 appears not to support this!!!So far everyone is suggesting I move back to SPC5Studio 5.8.1.So far not impressed with version 6 - Even the AI helps gets it wrong ! Currently just want to toggle some GPIO pins before moving on the CAN stuff, Currently using the SPC5884B70E5 device and using a SPC584B-DISP dev board to kick off our development. Hope someone can help 

Hey --  We would like to include a minimal version of .clang-tidy in our VS Code STM32 project. We use the STM32Cube clangd extension (through the STM32CubeIDE for Visual Studio Code Extension Pack). From our research it appears support for .clang-tidy is not currently included the STM32 fork of clangd. This request is to include that support.😎  Our expectation is that by adding a .clang-tidy file to the project root and --clang-tidy to the .vscode/settings.json (snippet shown below) we would begin to see output in the “Problems” tab and squiggles in the code base as we edit.~DigitalNomad{root}.vscode/settings.json (Win11)"stm32cube-ide-clangd.arguments": [        "starm-clangd",        "--compile-commands-dir=${workspaceFolder}/build/Debug",        "--clang-tidy", "--enable-config", "--background-index", "--completion-style=detailed", "--header-insertion=never",        "--query-driver=C:/ST/STM32CubeCLT_1.22.0/GNU-tools-for-STM32/bin/arm-none-eabi-gcc.exe"

Here is my main and jump to bootloader :int main(void){ HAL_Init(); SystemPower_Config(); SystemClock_Config(); HAL_Delay(500); // Catch bootloader constantly resetting jump_to_bootloader(); while (1) { HAL_Delay(50); }}#define BOOTLOADER_ADDR (0x0BF90000UL)HAL_StatusTypeDef jump_to_bootloader(void){ __disable_irq(); HAL_RCC_DeInit(); // Must be run before disabling systick because it depends on it HAL_DeInit(); SysTick->CTRL = 0U; // Disable systick SysTick->LOAD = 0U; SysTick->VAL = 0U; int count = sizeof(NVIC->ICER)/sizeof(NVIC->ICER[0]); for (int i = 0; i < count; i++) { // Clear pending interrupts NVIC->ICER[i]=0xFFFFFFFFUL; NVIC->ICPR[i]=0xFFFFFFFFUL; } void (*jump_to_bootloader_fptr)(void); jump_to_bootloader_fptr = (void (*)(void)) (*((uint32_t *) ((BOOTLOADER_ADDR + 4)))); __enable_irq(); __set_MSP(*(uint32_t *)BOOTLOADER_ADDR); jump_to_bootloader_fptr(); return HAL_ERROR; // Should never get there because of jump}

HiTrying to download the AutodevkitSW and unfortunately the page appears not to exist. Any help would be great

Hello everyone,I'd like to know if anyone has tried setting the size of the FLASH memory in a .ld file so that the unsafe zone is larger than the safe zone, for example, by changing the size of the unsafe zone .ld file to more than half the size of the flash memory and leaving the size of the safe zone .ld file at half the size of the flash memory.

Hello ST Community,I am working with an STM32F072RBT6 NUCLEO board and I am trying to generate3-phase complementary PWM using TIM1.My requirement is:• MCU: STM32F072RBT6• Board: NUCLEO-F072RB• Timer: TIM1• System Clock: 48 MHz• TIM1 Clock: 48 MHz• PWM Frequency: 20 kHz• Duty Cycle: 50%• Complementary PWM: CH1/CH1N, CH2/CH2N, CH3/CH3N• Required Dead Time: 500 nsMy TIM1 configuration is:Prescaler = 0Counter Mode = UpARR = 2399Clock Division = DIV1CCR1 = 1200CCR2 = 1200CCR3 = 1200PWM frequency calculation:PWM = 48 MHz / (PSC + 1) / (ARR + 1)PWM = 48,000,000 / 1 / 2400PWM = 20 kHzFor the dead time:TIM1 clock = 48 MHz1 timer tick = 20.833 nsRequired dead time = 500 ns500 ns / 20.833 ns ≈ 24Therefore I configured:DeadTime = 24My output pins are:TIM1_CH1  -> PA8TIM1_CH1N -> PB13TIM1_CH2  -> PA9TIM1_CH2N -> PB14TIM1_CH3  -> PA10TIM1_CH3N -> PB15The problem is with the complementary outputs.For example, when monitoring PA8 (CH1) and PB13 (CH1N) on an oscilloscope:• When PA8 is

I already built a project with my custom board and the stspin32g4 which works fine. Now I bought the EVLSERVO1 to evaluate higher power. But after successful code generation and flashing, motor pilot is not working ("Port Open, try to configure the board”) I already tested with another EVLSERVO1 board (because I thought my first one is broken). But second board same behavior.I checked, TX line from STLinkV3 ( 0x 85 FF FF BF) is sent but no answer from EVAL BoardI reduced Baud rate to 9600 because I thought maybe lost data because of high data rate. Maybe somebody can give me a hint. kind regardsPhilipp

Hi there.I have been asked to look at your eval board, EVALSTPM-3PHISO. The question is, i want to use Rogowski coils, can this board accept them or do i need another product.Many thanksIan

Hello everyone,I'm testing the use of trustzones in my application. The examples are working fine, however my application requires more FLASH in the non-secure zone than in the secure zone. The initial examples have the following parameters (default):The memory definition in the secure linker script is as follows:/* Memories definition - Secure Zone */MEMORY{ RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 320K FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 1016K FLASH_NSC (rx) : ORIGIN = 0x0C0FE000, LENGTH = 8K}The memory definition in the non-secure linker script is as follows:/* Memories definition - Non-Secure Zone */MEMORY{ RAM (xrw) : ORIGIN = 0x20050000, LENGTH = 320K FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 1024K}The Option bytes is as follows:So far it works. My application requires me to use 80K of memory in the secure zone and 1968K of memory in the non-secure zone, as I will show below:The memory definition in the secure linker script i

EnvironmentBoard: ATK-DLMP257B (STM32MP257), ST official Yocto image (X-LINUX-TSNSWCH) Kernel 6.6.48 deptp 2.5.2 (Flexibilis DE-gPTP Edge daemon) Driver: edgx_pfm_lkm (TTTech EDGE Platform Host Interface Driver)GoalConfigure the on-board switch as an IEEE 802.1AS Peer-to-Peer Transparent Clock, so that forwarded Sync/Follow_Up frames carry the residence time in their correctionField.Configuration (factory default, unmodified) <Interface name="sw0p2"><profile>gptp</profile><mode>tc</mode><delay>p2p</delay></Interface><Interface name="sw0p3"><profile>gptp</profile><mode>tc</mode><delay>p2p</delay></Interface><Basic><one_step_clock>0</one_step_clock></Basic>deptp.service is active. deptp_tool --get-tc-port-dataset returns valid data (faulty false, peer-mean-path-delay ≈ 145 ns), while deptp_tool --get-port-dataset returns error rejected — confirming that deptp is actuall

Hello,I generated a project using STM32CubeMX2 for Nucleo-C5A3ZG and I imported the project using the 'STM32CubeMX2 Project' option into STM32CubeIDE. I can compile and link the code without any issues however I noticed that there is only one build configuration (debug_GCC_NUCLEO-C5A3ZG for my project). Can STM32CubeMX2 also create a release  build configuration?My second related question what is the best way to add compile flags? I managed to add a -DDEBUG flag to the flags.cmake file and it works fine. Is this the right way to do it? Would project regeneration be troubled by this change?Finally, if I opted in for 'Assert checks on function parameters' and 'Assert checks on module state' in STM32CubeMX2 HAL System Init is there a way to only have this functionality enabled only for a debug build? Thank you,Gil 

Hello,I am using:Motor Control Workbench/X-CUBE-MCSDK 6.4.1 STM32G474RETx, 170 MHz EVLDRIVE102BH FOC with three-shunt current sensing A2212 13T, seven pole pairs I cannot find the High-Speed Observer, HSO, option in Motor Control Workbench.HSO is not visible or selectable in Motor Control Workbench. The same result occurs with a one-pole-pair, 24 krpm HKP Y0H0-A11 motor. Could you confirm:Is HSO publicly available in MCSDK 6.4.1? Is EVLDRIVE102BH supported? Which reference board should be selected? Is a particular MCU, motor type, sensing topology, or project type required? Is there a working HSO example project that I can import and run? Where exactly should HSO appear in the Workbench user interface?

My pc at work reboots itself whenenver I want to search something in a project (Crtl+h searching). I had windows 10 upgraded to windows 11 and that happened in windows 10 and later in windows 11. I formatted the pc and installed windows 11 from scratch. It still happens. And now, whenever I try to compile it reboots the pc too.If I check windows event monitor I usually see error 6008 unexpected event. Also I usually see error 41. Pc is new (about 2 years) and this does not happen with System Workbench, Visual studio or other eclipse ides I have in the same machine. Have you experienced this?

In TouchGFX 4.26.0 image order changes in application.config even if those images don't change.This causes unnecessary changes to show up in git: Feature request is to either preserve the order or to have them always lexicographically sorted.

I started a debug session on Cube IDE (version : 2.2.0) for my STM32F303 Discovery board.I got curious about GDB and I discovered that when I start a debug session, two GDB clients listening to the same GDB server are created. Why does it start two GDB clients?Task Manager ScreenshotTCP Connections to the GDB Server PortOne other confusion, whenever I start a new GDB client that listens to same GDB server, the console in Cube IDE prints the message “Waiting for debugger connection”. But when I monitor its TCP connection, I can see that its two gdb clients did not disconnect. And when I halt or resume the program execution or send gdb commands via the debugger console like “info registers” for exemple, it works fine. (I start my own GDB client by running the arm-none-eabi-gdb.exe executable)Console’s Message when I Start a New GDB ClientAny idea why the console print this message whenever a new GDB client connects to the GDB server?

I trying to follow the UFQFPN48 reference design for a STM32WB55CGUx in KiCAD.The ref design has some pinouts that don’t exist in the associated KiCAD symbol for the chip.The ref design, The KiCAD symbol with as much as I have wired up so far,  So the branch in the orange box for example, in the refence design this should have a branch just above C13 going to VFBSMPS yet in the KiCAD symbol this is missing. also there is no RF0.

This post is in response to the following post which has been closed so I am unable to reply...  Update – root cause found: STM32CubeProgrammer flash loader / FLASH_SR.PEMPTYI have finally found the cause of this issue and a reproducible workaround.The problem is related to the PEMPTY bit (bit 17) in FLASH_SR.On a failed debug/programming attempt I measured:FLASH_SR = 0x00020000 (PEMPTY = 1)SYSCFG->MEMRMP = 0x1SCB->VTOR = 0x1FFFF000PC = 0x1FFFxxxxThe MCU had therefore booted into System Memory rather than the application.On the next, successful attempt:FLASH_SR = 0x00000000 (PEMPTY = 0)SYSCFG->MEMRMP = 0x0PC = 0x0800xxxxThe option bytes were identical in both cases:FLASH->OPTR = 0xFFFF98AAI could reproduce this indefinitely: one programming attempt failed, the next worked, then failed, then worked.As a test, on a failed attempt I manually executed:set *(int*)0x40022010 = *(int*)0x40022010This changed FLASH_SR from:0x00020000to:0x00000000After subsequently resetting the

Dear forum,I am trying to setup a simple application to sample an ADC channel with DMA and stream it via UDP to a Windows PC, so here’s what I did:I started from the sample project “Nx_UDP_Echo_Client”, provided by ST in FW pack; I configured the ADC peripheral to sample pin PA1 as in the sample project “ADC_SingleConversion_TriggerTimer_DMA”, and this is ok; I configured the GPDMA channel 0 in circular mode to copy ADC.DR into a buffer, following this and this; I put the DMA buffer in a dedicated memory region (AHBSRAM1), as suggested here; I configured the buffer memory region as NON CACHEABLE in MPU configuration, as suggested here; Finally I configured the RISAF in order to let the GPDMA have access to the buffer, as suggested here.But still, when I try to activate the transfer with the HAL command HAL_ADC_Start_DMA, I get a “User setting error” (USEF bit in GPDMA_C0SR register) and the GPDMA channel is deactivated. Can you please help me in the debug?The project, which is attached

We are looking for Lowest Cost STM32 MCU with 32KB Flash and 12 KB RAM, 2 Uart, 1PWM, and 1 GPIO (No other requirments) for Mass Production requirement, Please help to choose.