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Hello,I would like to add Secure Boot + SFU functionality to my TouchGFX app with STM32N6. Since it is a graphics app, i don’t want to partition the external flash memory as installation and download slots as shown in the ST wiki for OEMuROT. https://wiki.st.com/stm32mcu/wiki/Security:OEMuRoT_for_STM32N6 To use external memory for apps and assests efficiently; below architecture is more suitable for me. Which changes are needed in the ST example ROT projects? With this, is it possible to debug the app code?                  Normal boot                      │                     ▼BootROM → Secure FSBL → verify App + Assets → HMI            Firmware update                      │                     ▼             USB / CAN                      │           signed package                      │                     ▼                Secure FSBL                      │     signature + version check                      │                 program NOR                      │                  verify

We would like to use the VL53L5 to measure the fuel level in a tank. According to the ATEX standard, the measuring device with the VL53L5 will be located near an opening in the tank in Zone 0.The datasheet does not specify the optical power of the circuit. The ATEX standard specifiesthe maximum optical power that the device may have in order to be installed in Zone 0. Could you please provide a table with the optical power values?

Hey, Guys!I’m designing an application to record TDM data source with 48k x 16 slots x 32Bit Format based on STM32MP151.But from the datasheet, there is some confusion.It seems the SAI supports 32bit and 16 slots from the SAI main feature description. But the FRL register is limited to 256, which cannot meet the requirement: 32*16 = 512 > 256.I’m using an external CODEC to generate the TDM clock, so STM32MP151 is in slave mode.Does anyone have experience with an application like this?Thanks!      Jampa.    

Environment & Hardware MCU: STM32F407ZET Test Temperature: -10°C to 5°C Application Context: Internal flash memory is actively used for data storage purposes When the MCU is interrupted specifically during an internal flash write operation (HAL_FLASH_Program)—either by a sudden VDD power-off or a hardware reset (NRST assertion)—it completely fails to boot upon the subsequent power-up or reset release. This issue is highly temperature-dependent and only occurs at low temperatures. If the interruption happens while the flash is idle, or if the board is at room temperature, the MCU reboots perfectly fine. Observed Symptoms & MeasurementsGarbage Vector Fetch: Attaching a debugger via hot-plugging shows that the CPU never reaches main(). Consequently, essential initialization routines like SystemClock_Config() and HAL_Init() are completely bypassed and fail to execute. Instead of fetching the correct reset vector from 0x08000004, the Program Counter is loaded with a garbage addr

Hello everyone, I have successfully controlled the Lin Engineering BL23E3301D04RO motor with the Nucleo-G474RE and IHM08M1 inverter .. using FOC configured in MC Workbench and the motor’s built-in encoder.I then copied the entire project and changed only the engine.Now I’m having trouble getting the following PMSM motor to run. Kt — 1.54 N·m/Arms Motor Constant Km— 1.63 Nm/sqrt(watt) RM (lin to line) at Amb — 0.60 Ohms Inductance — 2.24 mH Motor Poles — 16 Ipeak Motor — 51.19 Arms Tcont Stall — 20.74 N·m Icont Stall Motor — 13.60 Arms Tpk motor (25°C) — 64.54 Nm Rated speed — 1914 rpm Rated Power — 2826 W Inertia (KBM) — 5.69E-3 Kg-m² (4.20E-3 lb-ft-s²) Max Static Friction — 0.203 Nm (0.150 lb-ft) Cogging Friction — 0.102 Nm (0.075 lb-ft) Poles — 16 Back EMF Constant  — 93.3 Vrms/kRPM  In MC Workbench, I have set the following: I have configured the quadrature encoder to 2000 pulses per mechanical revolution. The power supply is CPX400S:Vout — 46V Iout,max

Hi, Following the original discussion here, this topic is split into a separate issue to remain aligned with Community guidelines and better visibility.DFU mode This processor can program the Option Bytes over DFU DFU ModeThis Processor is totally misdesignedIt exposes the Flash memory 3 timesFor me this looks like a severe bug.If you have a STM32G0B1 with read and write protection there is NO WAY over DFU get rid of these protections.

I’m trying to run a fork of the STM32N6-GettingStarted-ObjectDetection project for the STM32N6570-DK on my own board.My board has the same clock configuration, memory interface, and LCD interface as the STM32N6570-DK. However, instead of a CSI camera, I’m using an 8-bit parallel camera interface.The frames come from a custom FPGA source with the following parameters:75 MHz clock at 8 bit width bus YUV422 1280 × 768 30 fps Embedded synchronization ITU656My changes to the original project are:Added GPIO initialization for the 8-bit parallel camera interface. Changed the DCMIPP configuration from CSI to parallel mode:const DCMIPP_EmbeddedSyncCodesTypeDef syncСodes = { .FrameStartCode = 0xAB, /* frame SAV*/ .LineStartCode = 0x80, /* line SAV */ .LineEndCode = 0x9D, /* frame EAV */ .FrameEndCode = 0xB6 /* line EAV */};const DCMIPP_ParallelConfTypeDef pParallelConfig = { .Format = DCMIPP_FORMAT_YUV422, .VSPolarity = DCMIPP_VSPOLARITY_LOW, .HSPolarity = DCMIPP_

ST moderator: New question split from this thread: Thanks, that could indeed explain the behavior we are seeing, since we are powering Vdd with 3.3V.Since the application requires a stable ADC reference, I would like to ask whether the STM32L475 provides any internal precision reference that can be selected as the ADC conversion reference.

Hi ST Community,We are using the hardware CRC peripheral in our project for CRC computation.During system initialization, we initialize and configure the CRC peripheral ourselves. However, we observed that after calling MX_TouchGFX_PreOSInit(), the CRC peripheral appears to be re-initialized.We would like to understand how TouchGFX uses the CRC peripheral internally.Specifically:Does TouchGFX use the hardware CRC peripheral only during the MX_TouchGFX_PreOSInit() phase? Is the CRC peripheral used by TouchGFX during frame rendering or while processing/displaying frames? Are there any other TouchGFX phases, functions, or background operations where the CRC peripheral may be accessed? If both TouchGFX and our application use the same hardware CRC peripheral, could sharing the peripheral cause any issues?Our concern is that our application relies on a specific CRC configuration, and we want to ensure that TouchGFX does not modify or reconfigure the CRC peripheral after our initialization,

Hello everyone, I'd like to use the LevelX API with FreeRTOS on an STM32H5 microcontroller. I know that LevelX is typically used with AzureRTOS, but I'd like to know if ST provides any guidance on integrating it with FreeRTOS or if anyone has any suggestions on how I can do this. Thanks for your help.

While driving PMSM motor using STM32303E-Eval with IPM20B driver card, Motor is jerking and spinning abnormaly. I am using sensored feedback method such as encoder having 1024 ppr. 

Hi!I'm struggling to wrap my head around timers - I am trying to schedule some ADC reads of a current sense amplifier in a motor control setup.I have three center-aligned PWM waveforms being generated by Timer1, which successfully commutate a BLDC motor. That's great. I would now like to schedule an ADC read once per PWM period. A simple first try at this would involve a single read right in the center of the PWM waveform. A slightly swankier version would be to calculate the largest duty cycle of my three PWM phases, and schedule my ADC read just after this point (but, again, just once per PWM period). I have experimented with configuring Timer1's TRGO to "Update Event", and scheduling my injected ADC read to be "Timer 1 Trigger Out Event". This, however, schedules the read at the beginning of the PWM period, rather than in the center of it. I'm also experimenting with setting up a slave timer - the idea being to trigger this secondary timer based on the above Timer1 TR

On cubemx I could use the scroll wheel to pan and zoom, a brilliant feature which has been removed in mx2, can we have it reinstated as the app is very frustrating to use without it

On the STM32C542RC, this is my current FLASH layout:-- OEMiRoT flash layout:-- Bootloader : 0x08000000 .. +0x10000-- Keys : +0x10000 (0x2000)-- NV counters : +0x12000 (0x2000)-- Primary app slot : 0x8014000 size=0x16000-- App code (post-hdr) : 0x8014400 size=0x15c00-- Secondary app slot : 0x802a000 size=0x16000-- OEMiRoT option bytes to program:-- HDP1_END = 0x9 WRPSGn1 = 0xfe00Everything is working well (update of user application, boot, etc...) (MCUBOOT_USE_HASH_REF is not defined).But I have an issue:I want to use the external User Data Flash at the address FLASH_EXT_USER_BASE 0x08400000UL, requiring the option byte EDATA_EN = 0. When I read from that address in the User Application, I only read zeroes (RAZ) -- simple as `*(const int *)FLASH_EXT_USER_BASE == 0`, so this feels like the cause is some sort of HDP. By the way, the writes do work (at least when the MCU is reset, as STM32CubeProgramm

  When enabling USB_OTG_FS peripheral in Device_Only mode for STM32H743VIT6, CubeMX generates usb_otg.c with incorrect HAL macros:Generated (wrong) Should be (H7-native) GPIO_AF10_OTG1_FS GPIO_AF10_OTG2_FS __HAL_RCC_USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB2_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB2_OTG_FS_CLK_DISABLE  Root cause:  On STM32H7, the FS USB peripheral is USB2_OTG_FS, not USB1_OTG_FS. The H7 HAL defines GPIO_AF10_OTG2_FS for the FS port and GPIO_AF10_OTG1_HS for the HS port. CubeMX, however, generates F4/F7-style macro names (e.g. GPIO_AF10_OTG1_FS) which are only valid for MCUs with a single USB OTG peripheral.  Moreover, GPIO_AF10_OTG1_FS is conditionally defined in stm32h7xx_hal_gpio_ex.h only when USB2_OTG_FS is not defined. Since STM32H743 does define USB2_OTG_FS, the macro is absent at compile time.  The legacy compatibility aliases in stm32_hal_legacy.h could resolve this, but CubeMX does not include that header in the generated code.No

Hi, I wrote a flash bootloader for STM32G070 using IAR ide.It gets via modbus RTU the command/data to manage the FSM that does the update procedure.Because the master during erasing/programming needs a real time update on overall progression, the .intvec table, the main, the modbus stack and the updaing FSM are all relocated in RAM.With firmware in RAM and a management of FLASH delete/program via IT the firmware can handle modbus during flash programming.The .intvec relocation is done programmtically, copying it from FLASH (0x08000000) to RAM (0x20000000)  (0xB8 bytes):  I did via explicit firmware because I’m not able to do it via .icfAlso relocated in RAM  stm32g0xx_hal_flash*.o via “initialize by copy” in .icf.VTOR set to 0x20000000main entry point and other self-made function as well as modbus stack’s  marked as __ramfunc.Great, you say, if everyhing works why this topic? The truth is: to do all above I did a workaround  because a problem came when I linked HAL_FLASH_IRQHandler.Wit

Hi, I have been trying to implement the L6983 in my design for about 4 month now and still don’t get the desired output. After checking the Fsw pin, it seems I don’t get any clock output, do you have any idea what would be the cause of this issue ? Here is m design.The 0Ohm strips are only for a backup power supply. The Fsw output is flat on GND at the oscilloscope.The SW output before the inductor is at my supply voltage of 28V with small disconnects resulting in a flat 28V after the inductor.The input is 28V and it should output 5.2VThe switching method should be 500kHz without ditheringVs is delivered by a L6981 power supply + L39200 LDO at 3V3. This issue is present on several iterations of this design even though we made sure to reference the ST eDesign Suite for our choices.