Hello and good year everyone,I am trying to follow the architecture below, where I read 1 ADC halfword at 2KHz via SPI. The idea is to trigger the DMA 1 Channel 3 as soon a new data is available in my SPI. It transfers my data from SPI to RAM. As soo...

Hello everyone, Context :  I am having troubles chaining the DMA1 and MDMA of the stm32h755, more precisely, I am looking for the following data flow when reading data from SPI, the SPI being regularly triggered  :  SPI -> DMA1 Channel3 -> SRAM -> MD...