Posted on May 21, 2015 at 01:14It seems power pin on the generated pin assignments (especially pin 19 - 22) needs to be verified. Pin 21 should be VREF+ instead of VDDA?
Posted on February 27, 2016 at 11:42Thomas, I once had the same problem, it turns out my problem was the other circuit settings were incorrect, so the PHY was not working properly. After fix that problem, PHY reset wait loop had no problems. Hope it...
