About PatriceL

PatriceL · 2024-08-07

Hello happy taxpayers[EDIT #1]I forgot to say that what is really working is that is, from non secure app, I try to write in secure SRAM, then I end in the secure fault handler of my secure app. So, in this direction it's really clear the expected be...

PatriceL · 2024-07-26

Hi, I'm working on ADC1, on a STM32U5 (on a Nucleo board). In reference manual (RM0456) § 33.4.13 "Channel-wise programmable sampling time" we can read how to compute the total conversion time Tconv. The example is given for SMP = 5 ADC clock, at 55...

PatriceL · 2024-07-22

Hi,[EDIT 3] there is no need to configure GPIOC pin 0,1 and 2 as secure to be used by ADC1 since all GPIO are secure by default when TZEN = 1. cf. RM0456 § 3.5.6 "activating TrustZone security". This is why you do not find an of this in generated cod...

PatriceL · 2024-06-12

Hi community people, As an introduction, please note I'm completely new to the STM32 world, and back in embedded world after a long break in the application level. I now jump in a new project that will be based on a STM32U5, and I start digging in do...

PatriceL · 2024-08-13

yep, I have same reading as you. But, in the same time, as I spotted in my post, you can read this in STM32U5 reference manual: Any secure transaction trying to access nonsecure block in internal block-based SRAM or watermarked memory is considered a...

PatriceL · 2024-08-12

Hi @Roger SHIVELY , @fed For your information I have a similar issue, with SRAM : I can write to NS SRAM from S world where I expect it to fail. Here the post : My original post I did not try to read back what I wrote, this could be interesting to do...

PatriceL · 2024-07-26

Hi @STOne-32 and thank you for the confirmation. I've already read this pdf you mention, but did not pay enough attention to the table on page 16.So, this conversion time is fixed in number of clock, what is confusing is the sentences "for 14 bit" f...

PatriceL · 2024-07-23

Hi Jocelyn, and thank you for the tip: this is exactly what was wrong.This is consistent with reference manual RM0456, table 10 (page 159) that states when TZEN=1 then all SRAMs are both secured and privileged. What I forgot to do in MX is to set the...

PatriceL · 2024-06-13

Hi @Billy OWEN I did not expect my first post here was going to escalate this quick ;) . Thank you anyway to consider this.

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GTZC & illegal secure access failed to demonstrate: I can always write to non secure from secure

STM32U5 ADC1 : does conversion time depend on sampling time configuration ?

STM32U5 / Nucleo : ADC1 & DMA linked list and TrustZone: failed to sample, "USEF" DMA error

STM32U5 Nucleo where to find demo source code

Re: STM32U575 TrustZone access non secure area from secure mode

Re: STM32U575 TrustZone access non secure area from secure mode

Re: STM32U5 ADC1 : does conversion time depend on sampling time configuration ?

Re: STM32U5 / Nucleo : ADC1 & DMA linked list and TrustZone: failed to sample, "USEF" DMA error

Re: STM32U5 Nucleo where to find demo source code