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matsuami · 2024-05-06

There is a description in the errata(STM32G0B0CE/KE/RE/VE device errata) as shown below, but could you please provide a waveform diagram to show which part of the glitch is dangerous? USART2.10.1 Data corruption due to noisy receive lineDescriptionIn...

matsuami · 2024-06-11

Hello waclawek.janThank you for providing the excerpt from the reference manual.I could understand that in 2 stop bit mode, if there is no error in the first BIT, then readable normal data is written to the FIFO at that point.So, even if there is a g...

matsuami · 2024-06-06

Thank you for your valuable post.If we set it to 2stop bit mode, the number of bits in the communications protocol must be matched on the sender and receiver sides for communication to be established.That means the receiver also needs to be set, and ...

matsuami · 2024-06-03

Hello waclawek.janThank you for providing an example of the error.Best regards

matsuami · 2024-06-03

Hello　Imen.DThank you for your answer.I wanted the meaning of "he second half of the stop bit" clarified.In the case of a 2stop bit setting,① Is it the latter half bit of the first stop bit?② Is it the latter half bit of the second stop bit?③ Or is t...

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STM32G0B0CE/KE/RE/VE device errata

Re: STM32G0B0CE/KE/RE/VE device errata

Re: STM32G0B0CE/KE/RE/VE device errata

Re: STM32G0B0CE/KE/RE/VE device errata

Re: STM32G0B0CE/KE/RE/VE device errata