About heisenbug

heisenbug · 2024-03-27

Hi all,i see H7 supports clause 45 MDIO access, but in the HAL library looks not implemented, i see only clause 22.How should i proceed to read/write c45 ? Thanks,angelo

heisenbug · 2024-02-13

Hi all,i am performing some 400bytes blocks transferts by SPI, at 16Mhz.I have NSS off, so no CS up/down between frames.From some testing, whatever system clock i set, or whatever spi clock i set, there is a fixed 4us time between 2 consecutive frame...

heisenbug · 2024-03-27

Well, found now that the PHY chip i am using is supporting C22 to C45 bridge (multiple devices addressing), so don't need to add Clause 45 to HAL. Anyway, since h7 supports Clause 45, would be nice to have it imnplemented in HAL.

heisenbug · 2024-03-27

MDIO inside the ETH IP

heisenbug · 2024-02-22

Hi,i finally found out that delay between frames is due to the "transmit()" function os overhead, as @TDK correctly said in his first reply (i did this test initially moving mcu clock from 80 to 120Mhz, but probably i was not switching to 120Mhz at ...

heisenbug · 2024-02-15

no, looks like i cannot enable that "fifo-enable", i am getting some errors, it's a special fifo for st_stm32h7_spi

heisenbug · 2024-02-15

@waclawek.jan well, dma clocks are all disabled,also, i tried already to write constant values, there is not benefit.also, if it was a code overhead issue, increasing 30% the clock i should have see some benefit, while not happening.Anyway, i could h...

User statistics

User Activity

stm32h723zg Clause 45 MDIO

stm32L4S5, spi pause between 8-bit frames

Re: stm32h723zg Clause 45 MDIO

Re: stm32h723zg Clause 45 MDIO

Re: stm32L4S5, spi pause between 8-bit frames

Re: stm32L4S5, spi pause between 8-bit frames

Re: stm32L4S5, spi pause between 8-bit frames