STM32f103vet6It's in the manual that SDIO adapter clock (SDIOCLK = HCLK).  When HCLK is set to 72MHz, SDIO_CK is configured through the register SDIO_CLKCR bit 7:0(CLKDIV). When the bypass clock is not used, SDIO_CK=SDIOCLK/[CLKDIV+2], which should b...