Posted on May 17, 2018 at 11:08In RM0430 rev 7 section 6.2 it is stated that when TIMPRE is set and APB prescaler is 1 or 2 then the timer clock is HCLK.And when APB prescaler is > 2 then the timer clocks are HCLK * 4.This is different to the F446 w...

Posted on May 06, 2018 at 14:15On page 177 the definition of bits 4:0 and 12:8 of RCC_DCKCFGR appear to be incorrect.Should these be PLLI2SDIVQ and PLLSAIDIVQ respectively?