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chris239955_stm1_stmicro_com · 2019-06-03

chris239955_stm1_stmicro_com · 2018-10-28

Hello,I am working on the NUCLEO-L476RG board. I am trying to use two pairs of counters in master/ slave mode. In the first chain TIM2 is the master and TIM4 is the slave so in SMCR of TIM4 ITR1 is selected and this works as expected. In the second c...

chris239955_stm1_stmicro_com · 2014-08-25

Posted on August 25, 2014 at 09:18Hello,I am trying to use DMA to transfer data from a buffer in RAM to a GPIO BSRR port triggered by a timer. Due to the way the hardware is laid out I am committed to using TIM5 as the trigger. The DMA trigger is ...

chris239955_stm1_stmicro_com · 2019-06-04

Thank you for the links. Can you confirm that if we follow the BOM and copper traces and planes as shown in the Gerber files we can be confident of a compliant design?

chris239955_stm1_stmicro_com · 2018-10-29

Hello Imen,Why has the change been made to replace TIM5 with TIM15 on ITR2? I ask because this now makes STM32L series different from the STM32F series.I imagine it is too late to add a bit in an option register to make an option of either TIM5 or T...

chris239955_stm1_stmicro_com · 2018-10-29

In the timer section of the Reference Manual this is the information presented.I have been looking briefly through some of the Reference Manuals for STM32F family members and there is no Interconnection details section and I have always relied on the...

chris239955_stm1_stmicro_com · 2014-08-25

Posted on August 25, 2014 at 14:29Using TIM8 appears to be the only workable solution. The diagram I was looking at was ambiguous and I thought it suggested GPIO was accessible on both DMA channels

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We have been using the BlueNRG Tile in the STEVAL-STLKT01V1. The datasheet says there are reference design and layout details to implement our own circuit board. Where do we find the required information and what are the implications for compliance?

Master/Slave problem on TIM3 in STM32L476 - slave not counting when ITR2 selected

STM32F205 DMA Problem

Re: We have been using the BlueNRG Tile in the STEVAL-STLKT01V1. The datasheet says there are reference design and layout details to implement our own circuit board. Where do we find the required information and what are the implications for compliance?

Re: Master/Slave problem on TIM3 in STM32L476 - slave not counting when ITR2 selected

Re: Master/Slave problem on TIM3 in STM32L476 - slave not counting when ITR2 selected

Re: STM32F205 DMA Problem