Hi,I am looking on getting CM7 CPU Context backup inside Window Watchdog Early Interrupt handler (HAL_WWDG_EarlyWakeupCallback). The CPU context should include LR, PC, PSR, R0 to R3 and R12.Any help, example or code reference is appreciated.Thanks
Hi,We have build a custom board with STM32H745XIH6. I am using STLINKV3 debugger over SWD interface to connect to the target. When I connect to the board for the very first time, the STLINKV3 is able to connect at 24000 KHz clock using both STM32Cube...
Hi,I am working on STM32H745 discovery board and trying to configure the onboard 4GB eMMC flash over SDHC1 interface. I am loading default discovery board configuration by the CubeMx configuration, which sets both M7 and M4 and all AHB buses to run a...
I am working on STM32H7 (Cortex-M7) and using IWDG for monitoring. I am wondering if there is a way to record Cortex-M7 CPU registers (General Purpose (Rx), SP, LR and PC) when IWDG runs out. Either before or after the reset.I understand the RCC regi...
Hi,I am working on interfacing IS25LP128 128Mbit QSPI Flash with STM32H743 Nucleo board. I am running into problem with how the QSPI controller is driving the NCS line. The flash requires that the chip select remains low between command and data read...
There are various RAM blocks available in the MCU, and not all of the RAM are accessible by all DMA bus masters. For E.g. STM32H7 series, AXI SRAM is not accessible by BDMA. So if you try to use a data buffer from AXI SRAM (RAM Base address 0x2400000...
I got things working. Following are my findings.I still could not figure out the reason behind MMC/DMA example not working with 50MHz eMMC clock. But as I mentioned 25MHz clock works fine,The DMA issues were mainly related to the RAM being used for D...
