About Rob1

Rob1 · 2024-09-04

Hi to all.I have an H-bridge motor drive that I'm having some EMC issues with. There are always conflicting requirements. I want to drive the FET's hard , for power dissipation reasons , but faster gate rise times mean higher harmonic frequency gener...

Rob1 · 2024-02-20

Why does ST not provide a spice model for a new opamp. Specifically the TSB182 ?New parts should have a model.No model , not going to be considered for use.On another note ST's website is almost unusable. I get HTTP 408 and 504 errors almost every...

Rob1 · 2018-06-27

Posted on June 27, 2018 at 09:27STM32F051 ADC sample 5 channels with interrupt.I'm trying to sample 5 channels using an interrupt. (I'll get to DMA later:0))If I set the sample time to ('ADC_SAMPLETIME_41CYCLES_5') or longer then the code works as e...

Rob1 · 2016-12-12

Posted on December 13, 2016 at 06:46Hi all. I'm net to STM micros , so excuse the stupid question.I've set up USART1 on the stm32F0 discovery board, using the SPL , NOT cube.If I send data out the usart using the 'USART_SendData' function provided b...

Rob1 · 2016-11-01

Posted on November 02, 2016 at 07:41What is the actual data (x,y,z) length. When I'm reading the acceleration data , the lowest 4 bitsare 0. This would indicate the data is actually 12bit , left justified. The datasheet however say's the FIFO is 10b...

Rob1 · 2024-09-04

I'm not mixing up dithering and slew rate. I want a high slew rate to improve ( reduce) the power loss.High slew rate however results in higher harmonics and hence EMI/EMC issues.I want to dither the PWM to spread the harmonic frequencies over a wide...

Rob1 · 2024-02-27

Hi there , I did reply , but not sure what happened to it :0(I think they should say on the website that a spice model is in development. At least they you know that it is coming.It probably won't take long.CheersRob

Rob1 · 2018-06-27

Posted on June 27, 2018 at 12:38Some info to add to the question.If I make the ADC clock ('ADC_CLOCK_SYNC_PCLK_DIV4') , then I can set the sample time to a minimum of ('ADC_SAMPLETIME_41CYCLES_5').If the ADC clock is set to ('ADC_CLOCK_SYNC_PCLK_DI...

Rob1 · 2013-11-05

Posted on November 06, 2013 at 07:37Hi. I've managed to get timer4 working(sort of). It's difficult to debug when the SFR is not available in the debugger!!! I've sent a email to Atollic to see if I can get it resolved. The problem I'm having is the...

User statistics

User Activity

PWM dithering for noise mitigation

no spice model for new opamp? TSB182

STM32F051 adc interrupt problem. Multiple channels.

stm32F0 discovery and printf on usart

LIS3DHTR data length

Re: PWM dithering for noise mitigation

Re: no spice model for new opamp? TSB182

Re: STM32F051 adc interrupt problem. Multiple channels.

Re: STM32F102CBT6 Timer 4 question