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Why does PB9 idle high in reset for the STM32L4P5?  At least I'd like to know this the next time I design a board, where I could find this reference.  Full part is STM32L4P5RET although I'm guessing its the same across multiple parts.
Any ideas why values would be non linear in the approximately the upper 1 to 2 bits?For the setup below, it is linear to between -17000 to +14000. Doubling the + output only yields around +18000. These are raw values. This really acts like an overflo...
I'm using a STM32L4R9 with a W25G128, using non HAL code. The problem I'm seeing is that auto polling isn't stopped on match per logic analyzer. I have this set up to auto poll for write complete, register 0x05 busy bit 1. The match happens, I clear ...
Why in particular has the CMSIS freertos wrapper been chosen as the only option for the cubeMX ecosystem? Has there been any consideration to add a raw FreeRTOS API option to cubeMX?For an example of what seems iffy, see osThreadNew in cmsis_os2.c w...
What kind of reason would the DR register read the same on subsequent calls in release build?If I don't add __NOP()'s in there, the registers read the same and the FIFO doesn't get emptied.Micro is STM32F769NIstatic uint32_t drvInit(void) { uint32...
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