About _EFrie

_EFrie · 2025-03-10

Device is STM32F765VI.I'm using DMA to fill data allocated from DTCM, for some reason this seems to be caching.My understanding is that DTCM doesn't need cache management, help me if wrong here. If I don't enable the data cache everything works as e...

_EFrie · 2025-02-26

Using STM32F765, I'm using tim1 with OC toggle.The issue is glitches when I update the ARR value within the Repetition UP ISR. ARR Preload is enabled, not sure what to look at here.D2 toggles when the TIM1_UP_TIM10_IRQHandler fires, and D3 is TIM1 C...

_EFrie · 2024-07-22

Any suggestions as to why power down, then reconnect debugger (JLINK pro) is clearing the TAMP registers to 0?Device is STM32L4P5The clock source seems to be present, it doesn't enter the if statement if (LL_RCC_GetRTCClockSource() != LL_RCC_RTC...

_EFrie · 2024-07-15

Please forward vote against forced forum password resets due to expiration. It’s very old school security model.

_EFrie · 2024-07-12

Is there any known way to detect if a double word 0xffffffff value has been programmed? I’m not seeing any quick way, other than finding out after getting flash error bits set. The bootloader I’m working with checks the sector for all 0xff to avoid e...

_EFrie · 2025-03-10

Never mind, I didn't have the DMA write buffer in DTCM, please disregard question.

_EFrie · 2025-02-27

I think this was indeed a measurement error. I upped the sample rate and it seems to have gone away.

_EFrie · 2025-02-26

The counter isn't being cleared. yeah, its in the code there, but it turns off the timer completely, it only fires at the end.

_EFrie · 2024-07-12

Perhaps, but if you’ve been in programming long enough you know if it can happen it will, and needs a recovery mechanism in place. In this case what triggered this is a test binary with ff fill and something in upper bank to test firmware can write ...

_EFrie · 2024-07-12

Well, almost the same result, but for production I really want to be 100% sure that space is ready to write.

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DTCM cache DMA issue

ARR update causing output glitch

L4 TAMP registers resetting

Forced password reset

L4+ detect ff ecc already set

Re: DTCM cache DMA issue

Re: ARR update causing output glitch

Re: ARR update causing output glitch

Re: L4+ detect ff ecc already set

Re: L4+ detect ff ecc already set