Fig 9 of the STM32F429 datasheet it effectively states that the external source clock/signal has to be 1/3 of the Timer clock – makes sense as you want to ensure you capture the edge of the input signal. However, the Ref manual section 17.4.3, the re...

Posted on June 18, 2014 at 21:48Hey, I am looking for some working examples for the STM32F407 for the Ethernet, SPI, I2C, and USART. I have been using an STM32F4 Discovery board and an STM32F4 ETH Mountaineer board to evaluate the uP. But I have not...

Posted on June 12, 2014 at 00:53Does ST have any layout recommendations for using their Serial Wire Debug capability?  We are planning on using the Cortex M ETM debugging functionality.  This includes using the TRC CLK, TRC DATA[0], TRC DATA[1], TRC...

Posted on June 11, 2014 at 18:25Hey, I'm using the STM32F207VGT6. I see there is a duty cycle of 45%-55% on the input clock. Is this the same as the jitter spec- can the duty cycle chabge by 10% in a clock cycle and everything will still be OK? Cal...

Posted on April 08, 2014 at 01:04I have an STM32F215ZGT6 question.  When you put the processor into standby mode, the reference manual states that the GPIOs go into high-Z mode.  Does this mean that if you have a GPIO configured with a pull-up/down,...