I'm noticing lots of interrupts during reception of the last byte. Should there not just be one interrupt at the end of the last byte received?The top trace in the following screenshot shows entry/exit to/from the I2C Event ISR.
It seems the fix is trivial. Just don't enable the ITBUFEN interrupt in HAL_I2C_Master_Transmit_IT and HAL_I2C_Master_Receive_IT:The resulting bus capture looks perfect:It would be great if an ST engineer could comment on this and whether this is a s...
...or will RxNE remain set as long as the receiving shift register is clocking-in data? If so, should ITBUFEN be reset for the last byte so that we just get the one BTF interrupt at the end?
It looks like RxNE is not being cleared by reading DR?Here is the log of events (SR) during a 2-byte read from a sensor:[0] 0x00030001[1] 0x00030002[2] 0x00030040[3] 0x00030040[4] 0x00030040[5] 0x00030040[6] 0x00030040[7] 0x00030040[8] 0x00030040[9] ...
