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The DEVLNSTS[1:0] of OTG device status register seems to show a wrong logic level

Yang Yang
Associate II

Hello, ST experts

 

STM32U595VJT6 is used on the design. The OTG part of MCU works well on USB device mode. And it functions as USB flash disk.  But when I check the logical level from OTG device status register(address offset is 0x808), there is something wrong. If the USB cable is plugged in, it is all right, DEVLNSTS[1:0] are all zero. But when the USB cable is move out, DEVLNSTS[1] is 0, DEVLNSTS[0] is 1. That means USB_D+ is 0, USB_D- is 1. But the real logical level of USB_D+ is 1(about 3.3V), USB_D- is 0.

Am I missunderstand something?

 

Best Regards

Yang

1 ACCEPTED SOLUTION

Accepted Solutions
FBL
ST Employee

Hi @Yang Yang 

If I understand correctly, the device is configured in Full Speed (FS) mode, and the logic state of DEVLNSTS is not deterministic. Is that correct? It is preferable to provide full configuration of USB device.

Could you attach a trace of the USB traffic? Analyzing the USB traffic trace can provide insights into the communication between the host and the device, helping us identify any anomalies or patterns that might be causing the issue. 

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

View solution in original post

5 REPLIES 5
Yang Yang
Associate II

There is a update on this thread. The DEVLNSTS[0] is occasionally logic high level when USB cable is plugged in. (The possibillity is about 2%, 50 measures, 1 logical high, 49 logical low).

FBL
ST Employee

Hi @Yang Yang 

If I understand correctly, the device is configured in Full Speed (FS) mode, and the logic state of DEVLNSTS is not deterministic. Is that correct? It is preferable to provide full configuration of USB device.

Could you attach a trace of the USB traffic? Analyzing the USB traffic trace can provide insights into the communication between the host and the device, helping us identify any anomalies or patterns that might be causing the issue. 

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Hi, @FBL 

 

The divice is configured in High Speed Mode.  Yes, the logic stat of DEVLNSTS is not deterministic. Cube MX generate the code framework as the picture below. USBX and ThreadX are used in the software.

YangYang_1-1730077509939.png

For the USB traffic, because my oscilloscape is Tektronix MSO44 with a bandwidth of 500MHz, there should be some distortions about the signal measured.  The USB D+ waveform showes below during transmission.

IMG_20241028_091210.jpg

 

Yang

 

 

 

Hi, @FBL 

 

Another question about this thread. Does DEVLNSTS[1:0] represents the realtime logical level of  USB_D+ and USB_D-? There are very few discriptions about DEVLNSTS[1:0] on STM32U5's user manual.

 

BR

Yang

Yang Yang
Associate II

Hello

 

There is another update on this thread. It is found that the read of OTG_DSTS is not done on interrupts from the device all interrupts(OTG_DAINT) reigster. Is that the key issue?

And if it is so, why the DEVLNSTS[0](USB_D-) is always logical high state when USB cable is removed.

 

BR

Yang