About Handzic.Dirk

Handzic.Dirk · 2021-07-23

// InitialisationTIM1->PSC = (FOSC/(PWM_FREQ * PWM_STEPS)) - 1; // Timer clock TIM1->ARR = PWM_STEPS - 1; // Auto reload TIM1->BDTR = 0; // SafetyTIM1->CCER = 0;TIM1->CR2 = 0;TIM1->CCMR1 = ...

Handzic.Dirk · 2020-07-08

I want to use DMA to move data from memory to DAC1 channel 1 and channel 2. Channel 1 uses DMA Channel 5 and that works. CubeMX configured DAC1 Channel 2 for DMA1 Channel 6. The datasheet says STM32G431 is a category 2 device which has only channel 0...

Handzic.Dirk · 2020-07-03

Is there any DSP library for STM32G431? I would need a 1024 point FFT.

Handzic.Dirk · 2019-01-09

I have a problem on a STM32F071C board. The PLL will not reach ready state. I am using the HSI and in order to reduce current consumption I want to devide PLL from 8MHz down to 2MHz. This works fine on most board (18 out of 20) but on some the PLL_RD...

Handzic.Dirk · 2018-06-21

Posted on June 21, 2018 at 11:37The original post was too long to process during our migration. Please click on the attachment to read the original post.

Handzic.Dirk · 2021-07-23

Found the problem! The above code works but I thought the tDTG would be FOSC/PSC but it seems to be based on a higher frequency. How can tDTG be calculated?

Handzic.Dirk · 2020-07-10

I have found the problem! DMA CCR must access DAC peripheral by word.

Handzic.Dirk · 2020-07-09

Still have a problem, both DMA1 Channel 2 and Channel 3 now give an TEIF interrupt. Is there a limitation to use the same trigger for both DAC channels?? // DMA setup output 1 DMA1_Channel2->CCR = (DMA_CCR_PL_1 | DMA_CCR_MINC | DMA_CCR_PSIZE_0 ...

Handzic.Dirk · 2020-07-09

Thanks Jan, I have realized that and used the DMAMUX to assign DMA channels 2 and 3 to the DAC. I thought the CubeMX would generate code that could work on the selected microcontroller though.

Handzic.Dirk · 2020-07-03

Thank you! I will check them out.

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I am able to generate a complementary PWM signal. However due to hardware changes I would need to add a dead time. Regardless the value I am setting in the BDTR register there is no dead time at the output.

STM32G431C8

STM32G431 FFT

STM32F071C PLL never gets ready on some boards

STM32H743 dual ADC w DMA

Re: I am able to generate a complementary PWM signal. However due to hardware changes I would need to add a dead time. Regardless the value I am setting in the BDTR register there is no dead time at the output.

Re: STM32G431C8

Re: STM32G431C8

Re: STM32G431C8

Re: STM32G431 FFT