About baranovus

baranovus · 2024-10-11

Hello All.I want to disable RF write access for all the user memory. Do I have to use RFA1SS like: Write password 00000000;If security session is open: Read RFA1SS, OR it with mask 0x0C and write back to RFA1SS; Write password ffffffff.?Do I ...

baranovus · 2024-06-12

Hello All.Reading a register value from an I2C device assumes: Writing the device address-> Writing the register address without STOP-> Reading the value . I am trying to figure out if I can do it using only available HAL functions but I don't see h...

baranovus · 2023-07-02

Hello All.I wrote a simple code, which is supposed to start on reset address, check the availability of an application on the higher application address and jump to it. I am using IAR9.32. The code works if loaded using STLINK but gets into hard fa...

baranovus · 2023-05-16

baranovus · 2023-04-19

baranovus · 2024-10-11

Thanks!

baranovus · 2024-06-19

Thanks! That is the solution.

baranovus · 2024-04-17

Sorry, I found the answer at your attached pictures.

baranovus · 2024-04-17

May I ask: were you unable to set the bit in "SBS_ECCNMIR" or did you have the NMI in spite of it being set?Thanks

baranovus · 2023-07-11

The hard fault occurred in lz77 initialization code within IAR library after an attempt to access invalid RAM location. The issue disappeared after we changed the optimization level. It is definitely the IAR problem.

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ST25DV04KC disable RF writing

Reading I2c with sub-address

STM32H563 hard fault in low level init.

Hello. Should I be concerned about D-cache cleaning and invalidation in DMA functions on STM32H573? I am looking at the bus architecture and I see that DCACHE is connected only to OCTSPI and FMC unlike H7.

Hello. Is an STM32H5 reference design example with Ethernet available?

Re: ST25DV04KC disable RF writing

Re: Reading I2c with sub-address

Re: Disable Flash ECC NMI Issue

Re: Disable Flash ECC NMI Issue

Re: STM32H563 hard fault in low level init.