Our implementation of the SWIM protocol expects the "HSI clock is trimmed" bit in the SWIM CSR to be set after initialization. As UM0470 states, "At the end of the option byte loading, the HSIT bit in the SWIM_CSR is set by hardware."
In a test with STM8AL3188, we are finding that sometimes HSIT doesn't get set - the entry sequence works, the CSR can be read, but HSIT is not set within 10 seconds. What could cause this? Does it mean that option bytes are not loaded, or does this relate to UM0470, page 10, item 9: "Depending on the target context since power on, the HSI clock could be not well calibrated in step 4"?
