2023-05-16 02:59 AM
Hey
I have tried to use the option byte to stop the iwdg when i enter halt.
I can see that i manage to set the WDG_HALTin option byte 3.
But the watchdog still resets the MCU after i enter halt.
Please help me, cant i do it? If so then how do i read that from the documentation.
If i can what am i doing wrong?
I can reproduce the problem with this code:
void halt_test(void) {
// switch to 16MHz (default is 2MHz)
sfr_CLK.CKDIVR.byte = 0x00;
// Setup LED
sfr_PORTB.DDR.DDR2 = 1; // input(=0) or output(=1)
sfr_PORTB.CR1.C12 = 1; // input: 0=float, 1=pull-up; output: 0=open-drain, 1=push-pull
// Disable LED
sfr_PORTB.ODR.ODR2 = 1;
for (uint32_t i = 0; i < 600000; i++) {
NOP();
}
// unlock w/e access to EEPROM & option bytes
sfr_FLASH.DUKR.byte = 0xAE;
sfr_FLASH.DUKR.byte = 0x56;
// wait until access granted
while (!(sfr_FLASH.IAPSR.DUL))
;
// Enable write to option bytes
sfr_FLASH.CR2.OPT = 1;
// Set IWDG_HALT bit
sfr_OPT.OPT3.byte = 0b10;
// wait until end of programming
while (!(sfr_FLASH.IAPSR.EOP))
;
// Disable write to option bytes
sfr_FLASH.CR2.OPT = 0;
// lock EEPROM again against accidental erase/write
sfr_FLASH.IAPSR.DUL = 0;
// start IDWG (must be the first value written to this register, see UM)
sfr_IWDG.KR.byte = (uint8_t)0xCC;
// unlock write access to prescaler and reload registers
sfr_IWDG.KR.byte = (uint8_t)0x55;
sfr_IWDG.PR.PR = 6;
// set timeout period 0xff = 1724.63ms according to RM0031
sfr_IWDG.RLR.byte = 0xff;
// start IDWG
sfr_IWDG.KR.byte = (uint8_t)0xCC;
// Enable LED
sfr_PORTB.ODR.ODR2 = 0;
ENTER_HALT();
}
2023-06-06 02:32 AM
No worries, i just saw you listed as an employee i guessed you had access to the board.
Do you know how to get in contact with somebody at st that have access to the chip?
2023-06-06 02:42 AM
Unfortunately no, the only options are your local distributor or OnLine Support OLS where you can open a personal ticket.
However, the STM8 are already set to NRND (Not Recommended for New Design), so there are practically no resources left for this obsolete technology.
Good luck!
Regards
/Peter
2023-06-06 05:42 AM
Are you sure the watchdog resets while in halt?
Maybe program doesn't stop in halt.
2023-06-08 01:22 AM
I think i found the problem, but im not entirely sure why.
For start watchdog i set the KR register to CC in the code example. If i set it to AA instead everything seems to work as expected.
Would anybody know why that change would matter? I guess by reading the datasheet AA makes more sense but its not clear to me
2023-06-08 03:54 AM
Maybe value AA doesn't start watchdog. So reset doesn't occur.
From datasheet value AA starts watchdog, value CC refreshes watchdog.
2023-06-08 03:55 AM
Correction:
Maybe value AA doesn't start watchdog. So reset doesn't occur.
From datasheet value CC starts watchdog, value AA refreshes watchdog.