Entering Halt mode with the WWDG enabled causes reset

hloveland · ‎2011-07-15

Posted on July 15, 2011 at 22:39

I've checked the Option Bytes and the OPT3 byte is zero so the WDG_HALT bit is 0 which according to the data sheet means that the MCU should enter Halt Mode when calling halt() instead of generating a reset. Following the reset the RST_SR register is set to RST_SR_WWDGF indicating a WWDG reset. I'm wondering if there is some other condition causing the reset or is the description in the data sheet incorrect?

hloveland · ‎2011-07-18

Posted on July 18, 2011 at 18:35

It turns out that this isn't a problem with halt() but rather the side effect of a bug in RTC_AlarmCmd(). I was calling RTC_AlarmCmd(DISABLE) prior to calling halt() (I didn't want to go into Active Halt Mode) and the WWDG timeout was occuring while in the function RTC_AlarmCmd(). The problem is in this code snippet:

/* Wait until ALRxWF flag is set */

while ((alrawfcount != ALRAWF_TIMEOUT) && (temp1 == RESET))

{

alrawfcount++;

}

The line temp1 = (uint8_t)(RTC->ISR1 & RTC_ISR1_ALRAWF);

should be inside the loop or part of the while statement. As it is we always iterate 0xffff times and that's when the WWDG occurs.