Need to use SDRAM for heap and stack ans for that it needs to be up before main function

[shashank78Khandve]

I am working on SDRAM execution using FMC on STM32H563ZI (NUCLEO-H563ZI board) with external SDRAM connected through FMC interface.

Our target is:

1. Execute application sections from SDRAM
2. Place heap and stack in SDRAM
3. Enable automatic scatter-loading/copy from internal flash to SDRAM during startup

We are facing an issue where:

• SDRAM initialization appears successful
• Manual SDRAM read/write access works in application runtime
• But automatic copy/scatter-loading from Flash to SDRAM during startup is failing
• Application execution from SDRAM is unstable and leads to HardFault/reset handler

Below are the detailed steps and observations.

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1. CURRENT STARTUP FLOW

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Reset_Handler
→ SystemInit()
→ PLL/System clock configuration
→ FMC GPIO configuration
→ FMC SDRAM initialization
→ SDRAM command sequence
→ __main()
→ scatter loading
→ main()

We intentionally moved FMC/SDRAM initialization into SystemInit() so that SDRAM becomes available before scatter loading.

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1. CLOCK CONFIGURATION

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We configured PLL through direct register-level programming.

Configuration:

• HSE used as PLL source
• HSE = 25 MHz
• PLLM = 5
• PLLN = 36
• PLLR = 2
• SYSCLK = 90 MHz

PLL configuration registers used:

• RCC->PLL1CFGR
• RCC->PLL1DIVR
• RCC->CFGR1

We observed:

• System boots successfully
• main() is reached correctly
• FMC clock is enabled
• SDRAM initialization sequence executes

However, execution from SDRAM still fails.

We suspect there may be an FMC kernel clock stabilization issue immediately after SYSCLK switching from HSE/HSI to PLL.

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1. FMC GPIO CONFIGURATION

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All FMC pins are configured through direct register-level configuration (without HAL).

Configured pins include:

• Address lines A0-A11
• Data lines D0-D15
• BA0/BA1
• SDCLK
• SDCKE0
• SDNE0
• SDNRAS
• SDNCAS
• SDNWE
• NBL0/NBL1

GPIO configuration:

• Alternate Function AF12
• Push-pull
• Very high speed
• No pull-up/pull-down

GPIO clocks enabled:

• GPIOA
• GPIOC
• GPIOD
• GPIOE
• GPIOF
• GPIOG

FMC clock enabled through RCC->AHB4ENR.

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1. SDRAM CONFIGURATION

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SDRAM configuration:

• SDRAM Bank 1
• 16-bit data width
• 4 internal banks
• 8-bit column address
• 12-bit row address
• CAS latency = 3
• SDRAM clock period = 2 HCLK cycles
• Read pipe delay = 1

Timing configuration used:

• TMRD = 2
• TXSR = 3
• TRAS = 2
• TRC = 3
• TWR = 2
• TRP = 1
• TRCD = 3

These values are based on CubeMX-generated settings.

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1. SDRAM COMMAND SEQUENCE

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The following sequence is executed:

1. Clock enable command
2. Delay
3. Precharge all command
4. Auto-refresh command
5. Load mode register command
6. Refresh rate programming

Refresh rate currently configured approximately around:
683 (based on 90 MHz FMC clock)

---

1. MPU CONFIGURATION

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MPU region configured for SDRAM:

• Base address = 0xC0000000
• Size = 8MB
• Full access
• Non-cacheable configuration currently used for initial bring-up

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1. OBSERVED BEHAVIOR

---

Observed results:

• SDRAM initialization completes
• Manual SDRAM write/read test works after main()
• Direct pointer-based SDRAM access also works
• FMC registers appear correctly configured

However:

• Scatter loading to SDRAM during startup fails
• Application execution from SDRAM fails
• Heap/stack placement in SDRAM causes instability
• LED task execution eventually enters HardFault/reset handler

This suggests SDRAM works during later runtime but may not be stable during early startup/scatter loading.

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1. CURRENT SUSPICIONS

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We suspect one or more of the following:

1. FMC kernel clock stabilization issue after SYSCLK switch
2. SDRAM clock enable timing requirement not met during early startup
3. SDRAM stabilization delay insufficient before scatter loading
4. Additional startup sequencing requirement on STM32H563 FMC/SDRAM
5. Scatter-loading/runtime startup dependency before SDRAM becomes fully stable
6. Missing FMC/AXI/cache synchronization requirement
7. Requirement to keep stack/heap internal during scatter loading stage

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1. REQUEST FOR GUIDANCE

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We request support regarding:

1. Correct recommended startup sequence for SDRAM execution on STM32H563
2. Whether SDRAM initialization inside SystemInit() is officially supported
3. Any required stabilization delays before __main()/scatter loading
4. Any FMC clock synchronization requirements after PLL switch
5. Recommended MPU/cache settings for SDRAM execution
6. Recommended scatter file configuration for SDRAM execution
7. Whether any additional FMC initialization steps are required on STM32H5 series

Please let us know if you need:

• Full source code
• Scatter file
• SDRAM datasheet
• FMC register dump
• CubeMX project
• Debug screenshots

Thanks & Regards,

Shashank Khandve