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ethernet stopping.... after running 30 to 48 hours continuously.

Associate III

This reference is got from errata sheet of stm32h7. here they said some reason for related to my problem  . and they given problem description and workaround . but in code(cubeMX generated code for ethernet udp socket programming) where i should apply these conditions i did not understand . so plz can anybody  write (modify the hal functions) and share me the links or images of your modified code .  thanks,,,,,,


*---> Subsequent packets are not transmitted when the transmit queue is flushed during packet


When the transmit queue is flushed, the MTL layer completes the ongoing packet transmission and waits for a
status from the MAC layer. This status is provided to the application by updating the FF bit of the TDES0 transmit
descriptor word0. The MTL layer provides a dummy status with the FF bit set for every packet flushed in the
transmit queue. After the transmit queue flush operation is complete, the transmission restarts for packets
received from the application.
However, when the flush occurs during the second word of the packet being provided to the MAC layer, the
subsequent packets after the flush operation are not accepted for transmission by the MAC layer.


Make sure the Tx path is inactive before issuing a Tx queue flush command. To do this, follow the following steps:
1. Make sure the Tx DMA engine is inactive (either in the Stop state or Suspend state), and not fetching any
descriptor. To do this, stop the Tx DMA engine (by clearing the ST bit of the channel transmit control register
(ETH_DMACTXCR)) or ensure that the Tx DMA engine has serviced all the available descriptors, and is in
Suspend state. The state of the DMA engine is reflected in the TPS0 bitfield of the ETH_DMADSR register.
2. Make sure the Tx MTL is inactive. To do this, check that all the bits of the Tx queue debug register
(ETH_MTLTXQDR ) return 0.
3. Make sure the Tx MAC is inactive. To do this, check that all the bits of the MAC debug register
(ETH_MACDR) return 0.


Why do you think this erratum is pertinent to your problem?

Do you flush the Tx queue in your program?



Check what Jan said above.

I think even the HAL ETH drivers just don't flush the TX queue for fun.

Go through the code, line by line. Learn / understand what's going on.
What will you do with the next problem? Or when a new feature is needed?

ClickingCubeMX != HwDevelopment;


Associate III

---> that code is generated bu cubeMX ,, in that enabled the Tx queue flush

---> but if i dont flush the Tx queue , im getting ping problem (not pinging) 


HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
  uint32_t descindex = 0, counter;
  ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
  if(heth->gState == HAL_ETH_STATE_READY)
    heth->gState = HAL_ETH_STATE_BUSY;
    /* Set IOC bit to all Rx descriptors */
    for(counter= 0; counter < (uint32_t)ETH_RX_DESC_CNT; counter++)
      INCR_RX_DESC_INDEX(descindex, 1U);
      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
    /* save IT mode to ETH Handle */
    heth->RxDescList.ItMode = 1U;
    /* Enable the MAC transmission */
    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
    /* Enable the MAC reception */
    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
    /* Set the Flush Transmit FIFO bit */
  //  SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
/* Enable the DMA transmission */
    SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
    /* Enable the DMA reception */
    SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
    /* Clear Tx and Rx process stopped flags */
    heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
    heth->gState = HAL_ETH_STATE_READY;
    heth->RxState = HAL_ETH_STATE_BUSY_RX;
    /* Enable ETH DMA interrupts:
    - Tx complete interrupt
    - Rx complete interrupt
    - Fatal bus interrupt
                                   ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
    return HAL_OK;
    return HAL_ERROR;



That flush is done before DMA is enabled, so that should be okay.

Anyway, who said that this flush is the problem?

Have you enabled some / all the lwIP debugging options? There's a lot of debug info available.