Hello everyone,
I'm working on a project involving STM32's FMC specifically focusing on expanding memory capabilities. Given that each SDRAM bank (Bank 1 and Bank 2) can address up to 256 Mbit, I'm curious about the feasibility of integrating a single SDRAM chip with a larger capacity, specifically a 512Mbit chip with 13 address lines, such as the one detailed here:
https://www.issi.com/WW/pdf/42-45R-S-32160F.pdf
Is there a method or configuration within the STM32 FMC that would allow me to effectively use all of the 512Mbit SDRAM's capacity? or I have to use two 256Mbit SRAM with the individual clock and chip enable controls. Any insights or guidance on this would be greatly appreciated.
Thank you in advance for your assistance.
