STM32U575: How to configure the PB3 and the SWO to use ITM_SendChar in plain SWO debugging?

[PScal]

I want to use the SWO tracing without having the debugger configuring the SWO line, so that I can directly get the SWO events, by a proprietary own interface.

I already applied that code: (Still I get no output measuring with the oscilloscope.)

// based on https://developer.arm.com/documentation/ka001424/1-0/?lang=en
 
// Enabling ITM trace on Serial Wire Viewer
 
//
 
// Set TRCENA bit in Debug Exception and Monitor Control Register(DEMCR.TRCENA) to enable access to the trace components' registers.
 
 	SET_BIT(CoreDebug->DEMCR, CoreDebug_DEMCR_TRCENA_Msk);
 
// Select the required pin protocol in the TPIU_SPPR register:
 
//   0 - parallel synchronous trace port (not SWV)
 
//   1 - Serial Wire Viewer, Manchester encoding
 
//   2 - Serial Wire Viewer, UART Non-Return to Zero encoding
 
//  NOT needed default is manchester encoding
 
// Write 0xC5ACCE55 to the ITM's CoreSight Lock Access Register(ITM_LAR) to unlock the ITM. This register is missing from some editions of the processor's Technical Reference Manual (TRM).
 
  ITM->LAR = 0xC5ACCE55;
 
// Set ITMENA bit in Trace Control Register(ITM_TCR) to enable the ITM, together with additional bit fields in this register to enable timestamps, synchronization packets, and others as required.
 
 	SET_BIT(ITM->TCR, ITM_TCR_ITMENA_Msk);
 
// Enable the individual channels as required by setting bits in Trace Enable Register(ITM_TER0). You might also wish to control the privilege level of the stimulus channels by writing to the four least significant bits of Trace Privilege Register(ITM_TPR).
 
 	SET_BIT(ITM->TER, 1u);
 
// Set PI PB3 to use the alternative function AF0 (SWO)
 
	GPIO_InitTypeDef GPIO_InitStruct;
 
 
 
	/*Configure GPIO pin : */
 
	GPIO_InitStruct.Pin = GPIO_PIN_3;
 
	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 
	GPIO_InitStruct.Alternate = GPIO_AF0_TRACE;
 
	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 
	GPIO_InitStruct.Pull = GPIO_PULLDOWN;
 
	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
        
 
        ITM_SendChar('R');

When I use CubeIDE debugging having the SWO enabled, the character is send and I see the communication on the SWO line with the oscilloscope and the SWV ITM data console.

Does anyone has an idea what I miss?

[Diane POMABIA]

Hi @PScal​ 

some configurations are missing like :

-Enabling ITM trace on Serial Wire Viewer

-Select the required pin protocol in the TPIU_SPPR register

Please find my recommendation base on you code

// based on https://developer.arm.com/documentation/ka001424/1-0/?lang=en
 
// Enabling ITM trace on Serial Wire Viewer
  SET_BIT(ITM->TCR,ITM_TCR_SWOE);
//
 
// Set TRCENA bit in Debug Exception and Monitor Control Register(DEMCR.TRCENA) to enable access to the trace components' registers.
 
 	SET_BIT(CoreDebug->DEMCR, CoreDebug_DEMCR_TRCENA_Msk);
 
// Select the required pin protocol in the TPIU_SPPR register:
 // Choose your protocol for trace output by writing in  TPIU selected pin protocol register on bit TPIU_SPPR_TxMODE (option 1 or 2)
//   0 - parallel synchronous trace port (not SWV)
 
//   1 - Serial Wire Viewer, Manchester encoding
 
//   2 - Serial Wire Viewer, UART Non-Return to Zero encoding
 
//  NOT needed default is manchester encoding
 
// Write 0xC5ACCE55 to the ITM's CoreSight Lock Access Register(ITM_LAR) to unlock the ITM. This register is missing from some editions of the processor's Technical Reference Manual (TRM).
 
  ITM->LAR = 0xC5ACCE55;
 
// Set ITMENA bit in Trace Control Register(ITM_TCR) to enable the ITM, together with additional bit fields in this register to enable timestamps, synchronization packets, and others as required.
 
 	SET_BIT(ITM->TCR, ITM_TCR_ITMENA_Msk);
 
// Enable the individual channels as required by setting bits in Trace Enable Register(ITM_TER0). You might also wish to control the privilege level of the stimulus channels by writing to the four least significant bits of Trace Privilege Register(ITM_TPR).
 
 	SET_BIT(ITM->TER, 1u);
 
// Set PI PB3 to use the alternative function AF0 (SWO)
 
	GPIO_InitTypeDef GPIO_InitStruct;
 
 
 
	/*Configure GPIO pin : */
 
	GPIO_InitStruct.Pin = GPIO_PIN_3;
 
	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 
	GPIO_InitStruct.Alternate = GPIO_AF0_TRACE;
 
	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 
	GPIO_InitStruct.Pull = GPIO_PULLDOWN;
 
	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
        
 
        ITM_SendChar('R');

[Tesla DeLorean]

Make sure the GPIOB clock is enabled before configuring port. Also DBGMCU where appropriate.

Check baud / wire rate settings, been a while but depends on interface and SWCLK vs core clocking, as was impacted by connectivity with ST-LINK-V2/V3

Check if Segger has some scripts

[PScal]

@Community member​ and @Diane POMABIA​, thanks for the great suggestions.

I modified my code now finally to the following also with a hint given from Segger, but I still can't get the plain SWO to operate.

//	Enable traceing
//    DP->CTRL
    SET_BIT(ITM->TCR, ITM_TCR_SWOENA_Msk);
    uint32_t lu32_dbgMcuControl = DBGMCU->CR;
    lu32_dbgMcuControl |= (1u << 5u); // Clock the TPIU
    lu32_dbgMcuControl &= ~(3u << 6u); // Make sure SWO trace is enabled
    lu32_dbgMcuControl |= (1u << 4u); // Enable the trace pins
  	DBGMCU->CR = lu32_dbgMcuControl;
//  Set TRCENA bit in Debug Exception and Monitor Control Register(DEMCR.TRCENA) to enable access to the trace components' registers.
  	SET_BIT(CoreDebug->DEMCR, CoreDebug_DEMCR_TRCENA_Msk);
//  Select the required pin protocol in the TPIU_SPPR register:
//     0 - parallel synchronous trace port (not SWV)
//     1 - Serial Wire Viewer, Manchester encoding
//     2 - Serial Wire Viewer, UART Non-Return to Zero encoding
    TPI->SPPR = 1u;
//  Write 0xC5ACCE55 to the ITM's CoreSight Lock Access Register(ITM_LAR) to unlock the ITM. This register is missing from some editions of the processor's Technical Reference Manual (TRM).
    ITM->LAR = 0xC5ACCE55;
//  Set ITMENA bit in Trace Control Register(ITM_TCR) to enable the ITM, together with additional bit fields in this register to enable timestamps, synchronization packets, and others as required.
//  Set also Enabling ITM trace on Serial Wire Viewer
  	SET_BIT(ITM->TCR, ITM_TCR_ITMENA_Msk | ITM_TCR_SWOENA_Msk);
//  Enable the individual channels as required by setting bits in Trace Enable Register(ITM_TER0). You might also wish to control the privilege level of the stimulus channels by writing to the four least significant bits of Trace Privilege Register(ITM_TPR).
  	SET_BIT(ITM->TER, 1u);
//  Set PI PB3 to use the alternative function AF0 (SWO)
        __HAL_RCC_GPIOB_CLK_ENABLE();
 
        GPIO_InitTypeDef GPIO_InitStruct;
 
	/*Configure GPIO pin : */
	GPIO_InitStruct.Pin = GPIO_PIN_3;
	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
	GPIO_InitStruct.Alternate = GPIO_AF0_TRACE;
	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
	GPIO_InitStruct.Pull = GPIO_PULLDOWN;
	HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
ITM_SendChar('X')

Maybe it is not possible what I want to achieve any way. My need is to debug a bootloader development, and within this we use a page swap concept of the two flash banks, which is activated finally by a option byte load lunch operation, which uses a system reset. So far I ran into the trouble that this always resets also the debug interface and the CubeIDE losses the debug connection.

To overcome this, the idea I had was, to use the SWO and the ITM_SendChar and configure the SWO operation fully from within the STM32U575CI before using the first ITM_SendChar. And use the Segger J-Link SWOViewerCL with the option -swoattach 1 (not configure the debug interface by the JLink probe).