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STM32G0B0 timer3 LL_TIM_ClearFlag_UPDATE not clearing the Timer3->SR update bit.

Forum|Forum|3 years ago
May 19, 2023
8 replies
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STM32G0B0

STM32CubeIDE Version: 1.12.0

Segger JLink debugger

Moving from a STM32F micro with Standard Peripheral drivers to STM32G0B0 with Low Level drivers. Timer 3 is a simple configuration to interrupt and auto reload. After bring up the new processor the timer 3 is interrupting correctly but calls to clear the Timer Update flag(LL_TIM_ClearFlag_UPDATE(TIM3)) do not work. Because the Update flag is not clearing the interrupt is constantly triggering. The other strange thing is that the CCR interrupts seem to be on as well but they have not been configured.

Is it some simple configuration thing new to G0 micro's? (all this worked on the F0)

Configuration seems correct

	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3);
	
	// Timer 3 configuration. We want a timer 3 frequency of 2Khz(a interrupt
	// every .5msec
	tim_prescaler	= 0;
	TimOutClock		= SystemCoreClock/1;
	tim_period		= __LL_TIM_CALC_ARR(TimOutClock, tim_prescaler, 2000);
 
	TIM_TimeBaseStructure.Prescaler			= tim_prescaler;
	TIM_TimeBaseStructure.CounterMode		= LL_TIM_COUNTERMODE_UP;
	TIM_TimeBaseStructure.Autoreload		= tim_period;
	TIM_TimeBaseStructure.ClockDivision		= LL_TIM_CLOCKDIVISION_DIV1;
	TIM_TimeBaseStructure.RepetitionCounter	= 0;
	LL_TIM_Init(TIM3, &TIM_TimeBaseStructure);
	
	
	/* Enable the TIM3 global Interrupt */
	NVIC_SetPriority(TIM3_TIM4_IRQn, 1);
	NVIC_EnableIRQ(TIM3_TIM4_IRQn);	
	
	// Turn on the timer 3 interrupt enable and then enable timer 3.
 LL_TIM_ClearFlag_UPDATE(TIM3);
	LL_TIM_EnableIT_UPDATE(TIM3);
	LL_TIM_EnableCounter(TIM3);

This topic has been closed for replies.

Best answer by waclawek.jan

> The CNT registers are rolling

Timer keeps running even when the processor is stopped by debugger - except if you use the provisions of DBGMCU freeze registers (DBGMCU_APBx_FZ or similar). And, of course, running timer keeps setting the flags, too, including the Update flag, which is set each time CNT reaches ARR.

The CCx flags are set, as by default the CCx channels are set to Output with CCRx registers set to zero, so each time CNT goes to zero there's a Compare event. Setting of these flags is not "disabled" when bits in DIER are not set; it's the other way round: DIER bits being zero disable the status flags to trigger interrupts.

JW

waclawek.jan

Super User

Show content of all other registers of TIM3.

Is TIM3 stopped while you're observing its registers?

JW

CharlieMangoldAuthor

Senior

Yes we are in the interrupt 3/4 IRQ handler stopped just after the flag is supposed to be cleared(line #12 below.) The CNT registers are rolling and I've tried changing interrupt priorities but nothing yet. Just looking for other idea's at this point.

Thanks

void __attribute__((optimize("O0"))) TIM3_TIM4_IRQHandler(void)
{
 
	if (LL_TIM_IsActiveFlag_UPDATE(TIM3) != RESET)
	{
		timer3Tick++;
		LL_TIM_ClearFlag_UPDATE(TIM3);
		//WRITE_REG(TIM3->SR, ~(TIM_SR_UIF));
		//TIM3->SR &= 0xFFFFFFFE;
 
		// jpc, debug output for verification of timer3
		toggle ^= 1;
 
//		if (toggle)
//			GPIO_SetBits(GPIOF, GPIO_PF6);
//		else
//			GPIO_ResetBits(GPIOF, GPIO_PF6);
 
	}
 
}

CR1

CR2 & SMCR

Others

waclawek.janBest answer

Super User

> The CNT registers are rolling

Timer keeps running even when the processor is stopped by debugger - except if you use the provisions of DBGMCU freeze registers (DBGMCU_APBx_FZ or similar). And, of course, running timer keeps setting the flags, too, including the Update flag, which is set each time CNT reaches ARR.

The CCx flags are set, as by default the CCx channels are set to Output with CCRx registers set to zero, so each time CNT goes to zero there's a Compare event. Setting of these flags is not "disabled" when bits in DIER are not set; it's the other way round: DIER bits being zero disable the status flags to trigger interrupts.

JW

CharlieMangoldAuthor

Senior

I do understand that the timers continue to run but I have never seen the interrupt flag not clear in the debugger. Timer 3 is running at ~ 100usec so I don't see how stepping over the flag clear would not show up in the debugger. I could see it if the timer was running a very short period but I don't consider 100usecs that short.

The timer 3 DIER->CCxIE register description says the capture compare interrupt is enabled. So if the DIER bit is not set(not enabled), why am I getting flags set in the SR register when the timer triggers?

It seems like some kind of misconfiguration but the driver model we used was from a previous model of the board with a F series ST. Something about a M0+ core ?

waclawek.jan

Super User

Have you tried to set the DBG_APB_FZ1.DBG_TIM3_STOP bit, yet?

JW

CharlieMangoldAuthor

Senior

A write reg in the code seems to have no effect on the debug register. Do you need to do this from J-Link scripting or should this work?

Thanks

waclawek.jan

Super User

It may quite well be that the debugger (and by that I mean any component of the debug chain, including the IDE you are using) overwrites this register and/or prevents user from writing it. Try to browse the associated documentation.

[EDIT] It appears that you have to enable DBG clock by setting RCC_APBENR1.DBGEN first.

JW

CharlieMangoldAuthor

Senior

Just an update. I put in a pin toggle in the interrupt and timer 3 is running correctly. I've also checked the DMA interrupt ISR register bits and they clear in the debugger. So maybe this internal micro design which is different from the ST F series and leaves the timers running(and is not stopped by the J-Link), is timing out again before the debugger can read the ISR register.

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