STM32F401 CCR Interrupts all triggering at the same time

[MarcTaekema]

Hello,

I use the TIM5 on the NucleoF401 to compare 4 different moments with the CCR1 to CCR4 registers, However, all the interrupt flags seem to get set at the same time, 
I have added the initialisation and the interrupt handle for the timer below
I set the ARR value to 1,000,000 and have set all CCR1 values to be CCRx > ARR, this should have the effect of not triggering an interrupt ever until CCRx < ARR and CNT = CCRx 
This does not happen. As the interrupt flags are constantly set and reset for all CCRx registers. causing the interrupt to fire constantly. 

it seems to be that the interrupt flags are set when CNT = ARR, causing all CCRx register interrupt flags to fire at the same time. 

void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim){
	if (htim->Instance == TIM5) { // Ensure the interrupt is for TIM5
		switch (htim->Channel) {
			case HAL_TIM_ACTIVE_CHANNEL_1: // CCR1 triggered
				HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET);
				TIM5 -> CCR1 = 1001*UsToMs;
				break;
			case HAL_TIM_ACTIVE_CHANNEL_2: // CCR2 triggered
				HAL_GPIO_WritePin(GPIOA, GPIO_PIN_11, GPIO_PIN_SET);
				TIM5 -> CCR2 = 1001*UsToMs;
				break;
			case HAL_TIM_ACTIVE_CHANNEL_3: // CCR3 triggered
				HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, GPIO_PIN_SET);
				TIM5 -> CCR3 = 1001*UsToMs;
				break;
			case HAL_TIM_ACTIVE_CHANNEL_4: // CCR4 triggered
				HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6, GPIO_PIN_SET);
				TIM5 -> CCR4 = 1001*UsToMs;
				break;
			default: // Unknown or no active channel
				break;
		}
	}
	if(htim -> Instance == TIM2){
		switch (htim->Channel) {
			case HAL_TIM_ACTIVE_CHANNEL_1: // CCR1 triggered
				HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_RESET);
				TIM2 -> CCR1 = 1001*UsToMs;
				break;
			case HAL_TIM_ACTIVE_CHANNEL_2: // CCR2 triggered
				HAL_GPIO_WritePin(GPIOA, GPIO_PIN_11, GPIO_PIN_RESET);
				TIM2 -> CCR2 = 1001*UsToMs;
				break;
			case HAL_TIM_ACTIVE_CHANNEL_3: // CCR3 triggered
				HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, GPIO_PIN_RESET);
				TIM2 -> CCR3 = 1001*UsToMs;
				break;
			case HAL_TIM_ACTIVE_CHANNEL_4: // CCR4 triggered
				HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6, GPIO_PIN_RESET);
				TIM2 -> CCR4 = 1001*UsToMs;
				break;
			default: // Unknown or no active channel
				break;
		}
	}
}

static void MX_TIM5_Init(void)
{

  /* USER CODE BEGIN TIM5_Init 0 */

  /* USER CODE END TIM5_Init 0 */

  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
  TIM_MasterConfigTypeDef sMasterConfig = {0};
  TIM_OC_InitTypeDef sConfigOC = {0};

  /* USER CODE BEGIN TIM5_Init 1 */

  /* USER CODE END TIM5_Init 1 */
  htim5.Instance = TIM5;
  htim5.Init.Prescaler = 83;
  htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
  htim5.Init.Period = 1000000;
  htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  if (HAL_TIM_Base_Init(&htim5) != HAL_OK)
  {
    Error_Handler();
  }
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_TIM_OC_Init(&htim5) != HAL_OK)
  {
    Error_Handler();
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
  {
    Error_Handler();
  }
  sConfigOC.OCMode = TIM_OCMODE_TIMING;
  sConfigOC.Pulse = 1001000;
  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
  if (HAL_TIM_OC_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_TIM_OC_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_TIM_OC_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_TIM_OC_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN TIM5_Init 2 */
  HAL_NVIC_SetPriority(TIM5_IRQn, 0, 0);
  HAL_NVIC_ClearPendingIRQ(TIM5_IRQn);  // make sure that any pending interrupt is cleared
  HAL_NVIC_EnableIRQ(TIM5_IRQn);
  //TIM5 -> DIER |= (TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_CC3IE | TIM_DIER_CC4IE); //Enable interrupts for all CCR Channels
  //Timer starts using a function

 // HAL_TIM_OC_STOP_IT(&htim5, TIM_CHANNEL_1);
  //TIM5 -> CCR1 = 1001*UsToMs;
  //TIM5 -> CCR2 = 1001*UsToMs;
  //TIM5 -> CCR3 = 1001*UsToMs;
  //TIM5 -> CCR4 = 1001*UsToMs;
  __HAL_TIM_URS_DISABLE(&htim5);				//make sure that ARR can reset
  HAL_TIM_OC_Start_IT(&htim5, TIM_CHANNEL_1);
  HAL_TIM_OC_Start_IT(&htim5, TIM_CHANNEL_2);
  HAL_TIM_OC_Start_IT(&htim5, TIM_CHANNEL_3);
  HAL_TIM_OC_Start_IT(&htim5, TIM_CHANNEL_4);

  /* USER CODE END TIM5_Init 2 */

}

[waclawek.jan]

> it seems to be that the interrupt flags are set when CNT = ARR,

This is exactly their well documented behaviour. 

JW