GPIO alternate write acces? SPI CLK

[oeliks]

Hi! Do we have write acces on pin set to alternate function push-pull?

Problem: CLK line floats after hal_transmitreceive, pullup helps but distorts clk line.

And with pullup there seems to be a glitch at end that slave can detect as fake clock cycle and push MSB out of its scope and add to end radom bit.

Should i go with LL spi will this help?

Attachment: clk with pull-up, yellow - clk

 

[TDK]

CLK line should stay driven as long as the peripheral is enabled. Which chip? Show code.

[oeliks]

STM32H723 (genuine)

CubeIDE 1.14.1

Will post code tomorrow (I'm on night shift at the moment).

Do You want me to find and post here some specific part of code?

[Pavel A.]

Which STM32? Some models have a setting that releases SPI pins after a transaction. If this is your case, disable releasing the pins.

[oeliks]

Its STM32H723ZG

How to disable releasing the pins?

Master keep io state : enable ?

Or should I set AFCNTR in SPI_CFG2 (bit 31) "LL_SPI_EnableGPIOControl" in the LL library?

[Pavel A. · Accepted solution]

Yes exactly. Enable Master Keep IO state.

[TDK]

> Master keep io state : enable ?

This should work for what you want. When the SPI is disabled, the pins will still be driven.

[oeliks]

Thank You all for Your answers !

[oeliks]

This setting solved the problem.