DMA data alignment: zero-extension from 16-bit ADC to 32-bit memory on STM32H7

[davideggii]

Hello,

I am working with an NUCLEO-H753ZI (ADC1/ADC2 with DMA1/DMA2, and ADC3 with BDMA).
My goal is to store ADC conversion results directly into a uint32_t buffer using DMA, so that the 16 valid bits from the ADC are automatically zero-extended to 32 bits in memory.

The reference manual describes the possible data widths (byte, half-word, word) for peripheral and memory sides, but I could not find a clear statement about what happens when:

• Peripheral data alignment = half-word (16 bits)

• Memory data alignment = word (32 bits)

Does the STM32H7 DMA (DMA1/DMA2 and BDMA) guarantee that the upper 16 bits are always zeroed when transferring 16-bit peripheral data into 32-bit memory? Or are the upper bits undefined?

In CubeMX, when configuring ADC1 or ADC2 with DMA, it is not possible to set MemDataAlignment=WORD in the .ioc file (the tool only allows HALFWORD). Is this a CubeMX limitation, or does it reflect a real hardware restriction?

Thanks in advance for your support!

[waclawek.jan]

The ADC_DR is a 32-bit register, with the value of bits not resulting in conversion depending on several setting of the ADC, see Data management subchapter of the ADC chapter. And yes, some of the settings would result in 16-bit data right-aligned, with zero padding, see tables in that subchapter.

So word-to-word DMA would transfer just that.

If you'd use halfword at the peripheral side, the behaviour differs: DMA1/DMA2 are dual-port DMAs and they perform data packing (but only if FIFO is enabled), BDMA is a single-port DMA which zero-extends. See the respective DMA chapters in the RM.

JW