Time of erase after a tamper

[FAlca.1]

Hi all,

I am using MPU ref. STM32MP153F, do you say me what is the time that elapsed between a tamper is detected and the backup resister are finishing erased?

And the backup SRAM?

Thank you in advance

[PatrickF · Accepted solution]

Hi @Community member​ ,

Reference Manual answer to your questions.

Erase event is generated with the following latency:

• 3 ck_apre cycles when TAMPFLT differs from 0x0 (level detection with filtering)
• 3 ck_apre cycles when TAMPTS = 1 (timestamp on tamper event)
• No latency when TAMPFLT = 0x0 (edge detection) and TAMPTS = 0

Note that active tamper has obviously additional latency as clocked transitions.

Backup registers are erased immediately on erase event (let's says few ten of ns).

The backup RAM is not mass erased by an tamper event, instead it is read protected to prevent confidential data, from being accessed.

To regain access to the backup RAM after a tamper event, it needs to be first erased. (e.g. SW must write zero on the whole memory).

RAM.

Regards,

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