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TF-A getting error ERROR: Node system_off_soc_mode not found

JOhn1
Associate III

‎2022-06-07 12:59 AM

CPU: STM32mp153CAC

Problem:

CPU is unable to boot further because of error:

"ERROR:  Node system_off_soc_mode not found"

I have temporarily commented out the panic in the TF-A

This allows us to boot further into u-boot and then linux. But I'm worried that this is creating problems down the line.

We do not use STPMIC1 chip, can this be the reason for this error?

I suspect that something is missing in the device-tree. I have attached it.

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1 REPLY 1
JOhn1
Associate III

‎2022-06-07 12:59 AM 

/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
 * Author: STM32CubeMX code generation for STMicroelectronics.
 */
 
/* For more information on Device Tree configuration, please refer to
 * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
 */
 
/dts-v1/;
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include <dt-bindings/soc/st,stm32-etzpc.h>
#include "stm32mp15-mx.dtsi"
 
#include "stm32mp153.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15-ddr.dtsi"
 
/* USER CODE BEGIN includes */
/* USER CODE END includes */
 
/ {
	model = "Swarco custom board - openstlinux-5.10-dunfell-mp1-21-11-17";
	compatible = "st,stm32mp153c-itc3_cpu_a7_rev5-mx", "st,stm32mp153";
 
	memory@c0000000 {
		device_type = "memory";
		reg = <0xc0000000 0x20000000>;
 
		/* USER CODE BEGIN memory */
		/* USER CODE END memory */
	};
 
	/* USER CODE BEGIN root */
	/* USER CODE END root */
 
	clocks {
		/* USER CODE BEGIN clocks */
		/* USER CODE END clocks */
 
		clk_lse: clk-lse {
 
			/* USER CODE BEGIN clk_lse */
			/* USER CODE END clk_lse */
		};
 
		clk_hse: clk-hse {
 
			/* USER CODE BEGIN clk_hse */
			/* USER CODE END clk_hse */
		};
	};
	
	chosen {
		stdout-path = "serial0:115200n8";
	};
 
	aliases {
		serial0 = &uart4;
	};
 
}; /*root*/
 
&pinctrl {
	fmc_pins_mx: fmc_mx-0 {
		pins1 {
			pinmux = <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
					 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
					 <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
					 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
					 <STM32_PINMUX('D', 11, AF12)>, /* FMC_CLE */
					 <STM32_PINMUX('D', 12, AF12)>, /* FMC_ALE */
					 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
					 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
					 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
					 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
					 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
					 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
					 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NCE */
			bias-disable;
			drive-push-pull;
			slew-rate = <1>;
		};
		pins2 {
			pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
			bias-disable;
		};
	};
 
	sdmmc1_pins_mx: sdmmc1_mx-0 {
		pins1 {
			pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
					 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
					 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
					 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
					 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
			bias-disable;
			drive-push-pull;
			slew-rate = <1>;
		};
		pins2 {
			pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
			bias-disable;
			drive-push-pull;
			slew-rate = <3>;
		};
	};
 
	uart4_pins_mx: uart4_mx-0 {
		pins1 {
			pinmux = <STM32_PINMUX('A', 11, AF6)>; /* UART4_RX */
			bias-disable;
		};
		pins2 {
			pinmux = <STM32_PINMUX('A', 12, AF6)>; /* UART4_TX */
			bias-disable;
			drive-push-pull;
			slew-rate = <0>;
		};
	};
 
	/* USER CODE BEGIN pinctrl */
	/* USER CODE END pinctrl */
};
 
&pinctrl_z {
	/* USER CODE BEGIN pinctrl_z */
	/* USER CODE END pinctrl_z */
};
 
&bsec{
	status = "okay";
	secure-status = "okay";
 
	/* USER CODE BEGIN bsec */
	/* USER CODE END bsec */
};
 
&etzpc{
	secure-status = "okay";
	st,decprot = <
	/*"NS_R S_W" peripherals*/
	DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
	DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
	/*"Non Secured" peripherals*/
	DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_FMC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_DMA1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_DMAMUX_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_FMC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_UART5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_USART6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	/*"Secured" peripherals*/
	DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)
	/*"Mcu Isolation" peripherals*/
	DECPROT(STM32MP1_ETZPC_DMA2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
 
	/*Restriction: following IDs are not managed  - please to use User-Section if needed:
		  STM32MP1_ETZPC_SRAMx_ID  STM32MP1_ETZPC_RETRAM_ID  STM32MP1_ETZPC_BKPSRAM_ID*/
 
	/* USER CODE BEGIN etzpc_decprot */
		/*STM32CubeMX generates a basic and standard configuration for ETZPC.
		Additional device configurations can be added here if needed.
		"etzpc" node could be also overloaded in "addons" User-Section.*/
	/* USER CODE END etzpc_decprot */
	>;
 
	/* USER CODE BEGIN etzpc */
	/* USER CODE END etzpc */
};
 
&fmc{
	pinctrl-names = "default";
	pinctrl-0 = <&fmc_pins_mx>;
	status = "okay";
 
	/* USER CODE BEGIN fmc */
	/* USER CODE END fmc */
};
 
&rcc{
	status = "okay";
	secure-status = "okay";
	st,csi-cal;
	st,hsi-cal;
	st,cal-sec = <60>;
	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_HSI
		CLK_MCU_HSI
		CLK_PLL12_HSI
		CLK_PLL3_HSI
		CLK_PLL4_HSI
		CLK_RTC_LSI
		CLK_MCO1_DISABLED
		CLK_MCO2_DISABLED
	>;
	st,clkdiv = <
		1 		/*MPU*/
		0 		/*AXI*/
		0 		/*MCU*/
		0 		/*APB1*/
		0 		/*APB2*/
		0 		/*APB3*/
		0 		/*APB4*/
		0 		/*APB5*/
		0 		/*RTC*/
		0 		/*MCO1*/
		0 		/*MCO2*/
	>;
	st,pkcs = <
		CLK_CKPER_DISABLED
		CLK_FMC_ACLK
		CLK_ETH_DISABLED
		CLK_SDMMC12_HCLK6
		CLK_STGEN_HSI
		CLK_USBPHY_DISABLED
		CLK_SPI2S1_DISABLED
		CLK_SPI2S23_DISABLED
		CLK_SPI45_DISABLED
		CLK_SPI6_DISABLED
		CLK_I2C46_DISABLED
		CLK_SDMMC3_DISABLED
		CLK_ADC_DISABLED
		CLK_CEC_DISABLED
		CLK_I2C12_DISABLED
		CLK_I2C35_DISABLED
		CLK_UART1_DISABLED
		CLK_UART24_PCLK1
		CLK_UART35_DISABLED
		CLK_UART6_DISABLED
		CLK_UART78_DISABLED
		CLK_SPDIF_DISABLED
		CLK_SAI1_DISABLED
		CLK_SAI2_DISABLED
		CLK_SAI3_DISABLED
		CLK_SAI4_DISABLED
		CLK_LPTIM1_DISABLED
		CLK_LPTIM23_DISABLED
		CLK_LPTIM45_DISABLED
	>;
	pll2:st,pll@1 {
		compatible = "st,stm32mp1-pll";
		reg = <1>;
		cfg = < 3 24 1 1 1 PQR(0,0,1) >;
	};
 
	/* USER CODE BEGIN rcc */
	/* USER CODE END rcc */
};
 
&rtc{
	status = "okay";
	secure-status = "okay";
 
	/* USER CODE BEGIN rtc */
	/* USER CODE END rtc */
};
 
&sdmmc1{
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc1_pins_mx>;
	status = "okay";
 
	/* USER CODE BEGIN sdmmc1 */
	/* USER CODE END sdmmc1 */
};
 
&tamp{
	status = "okay";
	secure-status = "okay";
 
	/* USER CODE BEGIN tamp */
	/* USER CODE END tamp */
};
 
&uart4{
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins_mx>;
	status = "okay";
 
	/* USER CODE BEGIN uart4 */
	/* USER CODE END uart4 */
};
 
/* USER CODE BEGIN addons */
/* USER CODE END addons */
 

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