I am working on a design using the STM32MP257DAI3 and LPDDR4 memory. During the layout phase I was reviewing the routing guidelines from an5724. Section 6.3 recommends the following controlled impedances are required for the LPDDR4 interfaces:
- for single-ended signals: 55 Ω ±10%.
- for differential signals: 100 Ω differential ±10%
Can ST help me understand why they recommend 55 and 100 specifically for STM32MP257DAI3 with LPDDR4 and not 45 ohm single-ended and 85 ohm differential, which is what many 3rd parties seem to be proposing?
