I have a STM32MP157C-DK2, and I'm interested in better understanding how the IPCC peripheral works. I've tried out the OpenAMP echo example and trawled through its code, and the associated HAL code. I have generally completely avoided the HAL for microcontroller projects - I prefer to write my own bare metal drivers in C++.
IPCC seems like a very simple peripheral, but I am slightly confused by the implementation in HAL (and the Linux driver appears to do the same thing). When checking the RX/occupied status of a channel, both implementations read the SR register of the "other" processor. That is, the M4 uses the registers in IPCC_C2 to communicate, and the A7 uses IPCC_C1. But the M4 uses IPCC_C1->SR in HAL_IPCC_RX_IRQHandler(). What is the relationship between the two SR registers? It seems like in principle that they should have the same values, except maybe when transitioning.
My understanding is that if the A7 sets a channel bit using SCR, the M4 gets an RX/occupied interrupt; if the A7 resets a channel bit, the M4 get a TX/free interrupt. And vice versa. Is that correct?
Finally, is there a simple way to test my implementation? I just poke the ipcc driver directly in Linux, through sysfs or whatever, or am I basically going to have to re-implement RPMsg?
