2023-03-03 06:34 AM
I have a strange problem booting from eMMC (Kingstone EMMC04G-M627-X03U) on STM32MP153CAA Rev.Z.
By boot failure I mean fallback to serial boot (DFU over USB). Situation is as follows:
Attached Boot ROM traces (without and with primary/secondary sources set) and current OTP values. Any help appreciated, thank you!
Solved! Go to Solution.
2023-03-06 06:54 AM
Hi @Edgar A. Poe ,
In case your board did not use STPMIC1 for supply (which issue a power cycle on VDDCORE in case of reset), you should connect NRST to NRST_CORE with a 1nF capacitor as listed in ES0438 "Incorrect reset of glitch-free kernel clock switch" or AN5031 "Discrete supplies example 3.3 V I/Os with DDR3L"
Regards,
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2023-03-03 08:53 AM
2023-03-03 09:38 AM
eMMC is fully flashed and system is running correctly most of the time - problem appears occasionally when MPU is reset e.g. with Linux "reboot" command. I'd say now only one in ten reboots fail or even less than that. Pressing reset button or reconnecting power supply always helps and system boots correctly.
2023-03-06 06:54 AM
Hi @Edgar A. Poe ,
In case your board did not use STPMIC1 for supply (which issue a power cycle on VDDCORE in case of reset), you should connect NRST to NRST_CORE with a 1nF capacitor as listed in ES0438 "Incorrect reset of glitch-free kernel clock switch" or AN5031 "Discrete supplies example 3.3 V I/Os with DDR3L"
Regards,
In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'
2023-03-07 06:00 AM
Hi @PatrickF,
Thank you this helped to pinpoint the problem! We are using STPMIC1 but as a workaround for eMMC timeout issue on the previous prototype with Rev.B we had chosen much larger capacitor for the reset button just to keep MPU in reset for longer period at cold start. Now, because of this larger capacitor STPMIC1 very often did not register MPU reset and as a result did not make power cycle on VDDCORE and Boot ROM got stuck with incorrect clock.
2023-03-07 06:38 AM
Too long pulse on NRST could have been also solved by playing with RCC_RDLSICR.MRD field.
Don't know which value you had, but 10nF on NRST is still recommended and should work with default settings
Regards.